TSMC readies 55nm process shrink

March 27, 2007 – Taiwan foundry giant TSMC has unveiled its 55nm process technology, a 90% linear shrink process from its 65nm process which it says offers the same speed but uses 10%-20% less power than the prior process. The 55nm logic family for general purpose platforms will begin initial production this quarter (1Q07), followed by consumer platforms later in the year.

Since the 55nm process is a direct shrink, IP providers can use existing libraries and port their 65nm designs easily, the company said, noting that it “has already engaged many leading customers and IP suppliers on the process.” 55nm process runs on the company’s CyberShuttle prototyping program will continue on a bimonthly basis beginning in May.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.