April 24, 2007 – Cadence Design Systems Inc. says it has launched a 65nm reference flow for the Common Platform process developed by IBM, Chartered, and Samsung.
The Common Power Format RTL-to-GDSII reference flow, based on Cadence Encounter’s digital IC design platform, is designed to enable higher productivity and improved quality of silicon by addressing critical low-power design challenges, from chip prototyping through power, timing and area optimization, the company noted.
Technologies included in the flow include RTL compiler with global synthesis technology, test and power analysis, and timing system to reduce time to volume for low-power consumer applications. ARM low-power physical IP is also used for flow development.
“This 65-nanometer low-power reference flow provides an integrated methodology for customers to deliver low-power products in volume using CPF with the Common Platform technology,” said Jan Willis, Cadence’s SVP of industry alliances, in a statement.
“The delivery of this 65-nanometer reference flow makes available an innovative low-power design solution for Chartered customers,” added Kevin Meyer, VP of worldwide marketing and platform alliances at Chartered. Tom Lantzsch, VP of marketing, physical IP, ARM, noted that: “Working with the Common Platform technology partners and Cadence provides manufacturing flexibility along with advanced design solutions to accelerate time to market for our mutual customers.”