April 13, 2007 – IBM says it has developed a way to incorporate through-silicon vias (TSV) into its chipmaking process that shortens data-travel distances by up to 1000x and allows for 100x more pathways than 2D chips. Samples of chips using the 3D stacking technique will be shipped by year’s end, with production ramping in 2008.
IBM says it is fabricating a prototype SRAM design using 3D stacking technology and through-silicon vias with 300mm/65nm process technology, with samples starting in 2H07 and production in 2008. First products will be wireless communications chips in power amplifiers in wireless LAN and cellular applications. Future plans target high-performance server and supercomputer chips.
IBM says the 3D stacking technique offers the following benefits:
– Offers 40% better power efficiency in SiGe-based wireless products, and replaces less-efficient wire bonds for transferring signals off the chip;
– Increases processor speed while reducing power consumption by up to 20%, through uniform power delivery to all parts of the chip;
– Allows stacking of high-performance chips, e.g. processor-on-processor or memory-on-processor — e.g., the chip powering IBM’s Blue Gene supercomputer
IBM is one of many chipmakers pursuing 3D stacking technology. At IEDM in December, IMEC described how it has stacked and interconnected extremely thinned bulk silicon die containing through-silicon vias by direct copper-to-copper thermo-compression bonding, achieving functional through-silicon 3D-via chains. Meanwhile, NEC Electronics, Elpida Memory, and Oki Electric also have demonstrated a new 3D high-performance DRAM package using bumps and through-silicon vias. And a year ago, Samsung said it developed a wafer-level processed stack package (WSP) of high-density memory chips using “through silicon via” interconnections, that is 15% smaller and 30% thinner than an equivalent wire-bonded multichip package.
[IMAGE CAPTION: Cross-section image of IBM’s “through-silicon-via” technology in a stacked chip. (Source: IBM)]