April 23, 2007 – Samsung Electronics Co., Ltd., has developed an all-DRAM stacked-memory package using through-silicon vias (TSVs) housed in aluminum pads to avoid performance slow-downs caused by the redistribution layer.

The wafer-level-processed stacked package comprises four 512Mb DDR2 DRAM chips for 2Gbs of high-density memory. These DRAMs are stacked and interconnected with TSVs to for a 4GB dual in-line memory module (DIMM). In contrast to wire-bonding techniques, the proprietary technology forms laser-cut micron-sized holes vertically through the silicon and connects the memory circuits directly with copper filling. A proprietary wafer-thinning technique helped to eliminate warped die in the low-profile package, according to the company.

The performance advantages of WSP can benefit a mix of packaging solutions combining logic, memory, and other die, such as system-in-package (SiP) stacking logic on memory, said Tae-Gyeong Chung, VP of interconnect technology development in Samsung’s memory division, in a statement. The thinned, stacked die create a faster, smaller, and lower-power package, according to Samsung.

(Courtesy of SST sister publication Advanced Packaging )