Tessera interconnect platform targets limitations

IMAGE CAPTION: Addressing pitch limitation with µPILR technology.

Tessera Technologies Inc., launched an interconnection platform intended to address technical limitations of current-generation packaging technologies, such as pitch, profile, performance, reliability, and test capacity. The company expects this technology to become a fundamental building block of next-generation mobile, computing, and consumer electronic products.

The µPILR interconnect platform ¿ which stands for micro pin interconnect layer ¿ involves low-profile, pin-shaped contacts (25-175 microns high x 40-200 microns in pin-tip diameter) that replace conventional technologies, such as solder balls used in packages and plated vias in package substrates and PCBs. The result is a package with a reportedly reduced profile (contact pitches down to 100 microns), finer pitch (down to 0.3mm or lower for package-to-PCB, and 150 microns or lower within package substrates), improved electrical and thermal performance, and enhanced reliability, said Gordon Gray, senior product marketing manager.

To form an array of miniaturized pins directly on a substrate, manufacturing begins with a thin layer of copper coated with a very thin layer of nickel that acts as an etch barrier, followed by a thicker layer of copper to form a tri-metal substrate, explained Gray. The thick layer is etched back until it hits the nickel etch barrier, forming the pins. A laminate ¿ polyimide or FR4 ¿ is applied, and then the top layer is circuitized.

There’s a growing demand in the handheld-electronics market for smaller packages that are thinner, higher performance, and higher reliability, noted Gray. This technology is aimed at improving all of these areas. “We believe this is the next step in the interconnect evolution of advanced packaging,” he said, “for packaging applications we see this pin contact as a replacement for the solder ball. For package substrates it would be the replacement for the plated thru-vias that we typically see in substrates and PCBs.”

Gray said the first implementation of the technology is in the advanced packaging area ¿ to provide solutions for small die with low I/O or large die with high I/O. It will be applicable to single chip, multi-chip, package-on-package (PoP) stacking, and other configurations. One area of interest from hand-held manufacturers is application of logic plus memory package stacking with logic die on bottom, and different types of memory stacked on top.

Packaging assembly using this technology uses standard equipment such as die bonders and wire bonders, so assemblers can use existing tools and capital equipment. Gray says it may also allow for test and burn-in to be done without the need for socket pins, which would considerably reduce the cost of test.

In prototype, test and burn-in was completed successfully by placing a package pin-side-down in test housing so the pins met PCB pads. The lid was closed, applying a nominal amount of pressure. “We expect that the initial adopters of µPILR technology will still use conventional test/burn-in sockets,” says Gray, “however, as the evaluation stage of this feature is complete and the industry ramps to volume production, our goal is to enable a transition to socketless testing.”

Tessera is licensing this technology platform, and has been working with OEMS to enable a complete supply chain. “Our initial technical results on the stacking of multiple NAND flash devices in this low-profile packaging technology are promising,” stated Shozo Saito, corporate VP and executive VP of Semiconductor Company, Toshiba Corporation. Future plans include applications for substrate-to-PCB interconnect. — Fran


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