TSMC prepping 45nm ramp

April 9, 2007 – TSMC says it will complete 45nm qualification and enter production as early as September, ahead of initial 4Q07 plans.

The process, which utilizes 193nm immersion lithography, strained silicon, and extreme low-k intermetal dielectric materials, doubles the density of TSMC’s 65nm process, with “significantly lower power and manufacturing cost/die,” with 40% or greater functionality or 40% smaller die sizes, TSMC claims. The foundry’s general-purpose and high-performance process provides double the density with >30% speed enhancement vs. the previous generation at similar leakage power.

A low-power 45nm process will be first off TSMC’s lines, followed by a general purpose and high-performance process, and then a 45nm logic family with low-power triple gate oxide option. TSMC says it has already delivered functional chips from its first 45nm CyberShuttle prototyping program, with “a double-digit number of companies” using the service along with several IP vendors. Three more CyberShuttle runs are scheduled for May, August and December.


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