April 5, 2007 – Virage Logic has developed silicon proven, high-density SRAM memory using TSMC’s 65nm general-purpose plus process, targeting system-on-chips.

The test chip, based on Virage’s “Silicon Aware Self-Test and Repair” (STAR) memories, enables both high-speed and low-speed coverage, employing high memory densities to replicate conditions that produce yield challenges in production volumes, the companies stated.

The two firms have created a sub-90nm collaboration model to address SRAM design from bit-cell design to silicon validation, pioneering the proprietary STAR test chip methodology to ensure robustness in a SoC context for functionality, performance and yield. They plan to further develop silicon validation for Virage’s Area, Speed and Power (ASAP) Memory and Self-Test and Repair (STAR) memories, and ASAP Logic product families for TSMC’s future technologies.