Ziptronix 3D interconnect tech targets multilayer CMOS ICs

April 5, 2007 – Ziptronix Inc. and Raytheon Vision Systems (RVS) say they have demonstrated compatibility of Ziptronix’s “direct bond interconnect” (DBI) interconnect technology with multilayer CMOS IC processes, involving 3D integration of five-layer metal 0.5-micron CMOS devices with silicon PIN detector devices.

RVS parts were built in a die-to-wafer format (DBI also supports wafer-to-wafer format) with 8-micron interconnect pitch. The majority of initial device yields were 100% for parts with >1M vertical connections, the companies said in a statement. Targeted application is high-performance imaging including focal plane imagers and sensor arrays.

“With the Raytheon project, we successfully applied our planar DBI technology to achieve a very high 3D integration density with a multilevel CMOS process,” said Paul Enquist, Ziptronix CTO and VP of R&D.

The DBI interconnect technology achieves high-density vertical interconnections without volume exclusions, supporting >10-micron pitch and typical width of 2 microns and 1-micron alignment accuracy, the company says. Enquist noted that the technology utilizes existing equipment operating at room temperature without applying external pressure.

In Oct. 2005 the company said it had developed a 3D system-on-chip combining memory, microprocessor, and programmable logic die into a single multilevel silicon die as a demo for a customer for use in wireless communication applications.


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