May 3, 2007 – IBM Corp. is touting a two-generation performance improvement with what it claims is a new technique that self-assembles vacuum “airgaps” to insulate wiring connecting transistors.
“This is the first time anyone has proven the ability to synthesize mass quantities of these self-assembled polymers and integrate them into an existing manufacturing process with great yield results,” said Dan Edelstein, IBM Fellow and chief scientist of the self-assembly airgap project.
The achievement skips the typical masking and light-etching steps involved with laying down insulating layers, the company claims in a statement. Instead, the new method involves mixing and pouring a specific blend of compounds onto a patterned silicon wafer, which is then baked. The compounds self-assemble in a directed manner, creating trillions of uniform (20nm-dia.) holes across the entire 300mm wafer. Once the holes are formed, the carbon silicate glass is removed, creating a vacuum between the wires, what IBM is calling “airgaps.”
IBM says lab tests on chips utilizing the technique show 35% faster electrical signal flow, or 15% more efficient energy consumption, “compared to the most advanced chips using conventional techniques,” adding that the technology can be added “into any standard CMOS manufacturing line, without disruption or new tooling.”
IBM says it has created experimental versions of its latest POWER6 microprocessor using the self-assembling technique. The process has been integrated into lines at East Fishkill, NY, and IBM expects to use it starting in 2009 with server chips, and later in products for other companies.
The new process was jointly developed by researchers at IBM facilities in San Jose, CA, and Yorktown, NY, and tweaked for commercial production at the U. at Albany’s College of Nanoscale Science and Engineering.