By Phil LoPiccolo, Editor-in-Chief
Among the most significant developments in interconnect to look for at the upcoming International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) involve 3D chip architectures. Sitaram Arkalgud, director of SEMATECH’s interconnect division and its newly created 3D interconnect initiative, calls 3D chip architecture his “new religion,” because stacked chips allow interconnects to be much shorter than in traditional 2D configurations. This technique, he claims, could be the most promising route to reducing resistance-capacitance (RC) delays, the main stumbling block to higher chip speeds and lower power consumption.
Traditional approaches to reducing RC delays face serious obstacles. For instance, lowering the relative permittivity (k value) of the dielectric materials surrounding metal interconnect lines, in order to reduce the signal-retarding capacitive coupling that occurs when the lines are placed closely together, has progressed more slowly than the International Technology Roadmap for Semiconductors (ITRS) timetable has specified, explained Arkalgud, and that trend could continue — at the 32nm node, the ITRS calls for keff to be between 2.1-2.4, he noted. The problem is that lowering the k value, typically by adding porosity, means the mechanical properties of the materials (hardness, elastic modulus, etc.) all go in the wrong direction, and damage resulting from etch, ash, and CMP processes needs to be eliminated. Also, the use of low-k support layers (etch stop, caps, hard masks) is essential to realize the low-keff value). Consequently, expensive new tools, such as low-downforce CMP, must be integrated into process flow to compensate for the more fragile materials.
Similarly, reducing resistance in interconnect lines has proven difficult. As copper wires are made thinner, resistivity rises because of volume effects and surface and grain boundary electron scattering, “and there’s little we can do about it, because we’re bumping up against physics,” Arkalgud noted. Moreover, process variations at that scale compounds the problem of controlling line resistance.
“Clearly, we’re up against some big issues in reducing interconnect resistance and capacitance,” says Arkalgud. “While copper and low-k will remain the metallization of choice for most companies, it will be harder to realize the RC benefits of material and linewidth scaling.” So, SEMATECH has turned its attention to the most promising future directions for meeting these challenges, including 3D chip architectures with through-silicon vias, carbon nanotubes, optical interconnects, and guided waves. “And in our opinion, 3D stacking using through-Si vias stood out, for several reasons,” said Arkalgud.
Advantages of 3D
One benefit of 3D stacking is improved performance. “To take interconnect lines, which can be several mm long, and turn them into vertical interconnects that are only 10s to 100s of microns in length, you can significantly cut down the RC delay in a brute force kind of way,” says Arkalgud.
Another advantage is that, for the most part, no new materials would need to be developed and integrated, Arkalgud explains. Apart from the bonding material, 3D stacking uses mostly standard silicon processing.
3D stacking also enables greater integration of heterogeneous layers of functionality, such that any combination of logic, memory, analog, MEMS, sensors, optoelectronics, and bio-devices could be incorporated into the stack.
In addition, from a cost perspective, the most economically feasible processes could be used for each layer of a heterogeneous 3D chip architecture. For example, for some layers (such as analog and low performance logic), a chipmaker might use a depreciated fab running 0.25-micron technology, and run a high performance logic or high-density memory in a state-of-the-art, 65nm fab, and then bring all the layers together in the 3D stack, Arkalgud says. That could avoid the cost issues with system-on-chip (SoC) designs, in which chip manufacturers pay for cutting-edge processes for the entire chip, even for blocks with significantly lower technology requirements.
Among papers released in advance of IITC that discuss advances in 3D chip interconnects is one from IMEC researchers, describing how they created 3D chip stacks with improved thermal and mechanical stability by using both copper-to-copper thermocompression bonding and compliant glue layer bonding. The glue layer, which had no impact on the resistance of through-wafer via test structures, allowed separate die-stacking and die-bonding operations. That way, a landing wafer can be populated with dice in a fast pick-and-place operation, then the dice can be bonded collectively later on (see image above).
Another 3D architecture paper, from a Freescale and Leti teamresearchers, explains how they created 3D circuits using a dielectric-to-dielectric wafer bonding process and 90nm low-k interconnect technology. The researchers team reports that the integration technique depends strongly on keeping the respective surfaces clean to ensure reliable, defect-free direct dielectric bonding, as well as precise wafer-to-wafer alignment, backside thinning, and deep through-strata via formation.
Other technologies: CNT, optical, waves
Additional advance-released IITC papers focus on the other leading interconnect technologies that Arkalgud and his team at SEMATECH have been evaluating: carbon nanotubes (CNT), optical interconnects, and guided waves.
On the CNT front, a team at MIRAI-Selete in Japan reports it has designed a mostly CMOS-compatible damascene process for fabricating vertically aligned, multi-walled nanotubes, with 10nm dia. and a density of 3×1011/cm2 in 160nm dia. via holes, and with the lowest resistance (0.05 ohms) reported to date. (See “CNT interconnects target 32nm”, WaferNEWS V14n17, April 24, 2007). In other CNT work, a team from RPI has developed a novel technique to significantly increase the density of CNT bundles, and thereby reduce their resistance, by immersing CVD-grown, CNTs in an organic solvent. When the solvent evaporates, the individual nanotubes aggregate into higher-density bundles by capillary coalescence and remain together by van der Waals forces.
In the realm of optical interconnects, Sun Microsystems researchers have devised a 90nm test chip that integrates optical interconnects employing external lasers and photodiodes with two other types of chip-to-chip interconnects: capacitive interconnects for proximity communication and electrical interconnects using current-model logic for high-speed operation and optical compatibility. The researchers report interoperability between all three interfaces at speeds exceeding 2.5 Gbps, and contend that the work could drive more aggressive interconnects including silicon-based photonics (see image below).
Developments in guided wave interconnect technology are reported in a paper by a Tokyo Institute of Technology team that has built a low-voltage transmission-line interconnect architecture based on a 90nm silicon CMOS process, that transfers signals as electromagnetic waves, using on-chip inductors as transceivers. The team achieved 10Gbps signal transmission with 2.7mW power consumption, and reports that delays were reduced by up to 89% compared to a conventional interconnect stack. — P.L.
CAPTION FOR TOP IMAGE:
At IITC, IMEC researchers will describe how they used copper-to-copper thermocompression bonding with a spin-on compliant dielectric glue layer to create 3D systems with improved thermal and mechanical stability. The illustration shows two thin ICs (IC2 and IC3) stacked on a third device (IC3), with dice separated by a thin dielectric glue layer and integrated with through-silicon copper vias. (Source: IITC, IMEC)
CAPTION FOR BOTTOM IMAGE:
At IITC, Sun Microsystems researchers will describe a 90nm test chip integrating three types of chip-to-chip interconnects: capacitive interconnects for proximity communication, optical interconnects employing a vertical cavity surface emitting laser (VCSEL) and photodiode (PD), and electrical interconnects using current-model logic for high-speed operation and optical compatibility. The illustration shows how these pieces might fit together. (Source: IITC, Sun Microsystems)