New challenges for chip package interaction

by Bob Haavind, Editorial Director, Solid State Technology

While chip-package interaction (CPI) has always been important, new challenges are emerging as the industry goes to system-in-a-package (SiP) and new materials, according to Mitsuharu Shimizu, GM, R&D div., Japan’s Shinko Electric Industries.

The legacy functions of packaging remain, such as protecting the silicon, standardization, electrical connection, and so on. But system-in-a-package (SiP) often brings new requirements, moving from a single chip to multiple chips, from a simple dc connection to a need for signal integrity margin, and more flexibility to fluctuating demand on the circuitry. As an illustration, Shimizu showed how much smoother resin coatings are needed to ensure signal integrity in an SiP.

The trend toward low-k or even ultralow-k interconnect dielectric also brings many new considerations. There may be many players involved in compensating stress, for example, involving such factors as the chip structure, bumps, underfill, substrates, and process temperatures. The solution for one device is often not the best for a different one. Collaborative evaluation can be effective, he suggested, in finding a focal point and solution for each case. He showed examples of stress after die attach and stress after an underfill cure to illustrate the types of problems that have to be solved.

Electromigration can be a problem with flip-chip connections, according to Shimizu. There are multiple technology transitions increasing potential problems, such as reducing the flip-chip interconnection pitch, higher current density, requirements for lead-free solder, and so on. Solutions must provide reliability initially and over time. Common test procedures, allowing accelerated testing, should be helpful for all parties involved, he said. — B.H.


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