I’ve always thought that packaging was sexy. Can’t you just imagine a movie where a person leans over to whisper, “Talk packaging to me”?
And, it’s newsworthy. In the front-end, the biggest news is moving to 300-mm wafers so that you can do more of the same thing with the same materials using similar equipment.It’s too expensive to change the whole process, and costs are already established. However, in packaging, the playing field is wide open. Where cost is king, advanced packaging represents an area of creativity and cost control. Any package that works reliably at lower cost with excellent thermal control is one that will grow.
Take Amkor Technology, Inc., which introduced package-on-package (PoP) in 2004 as a stackable, very thin, fine-pitch BGA (PSvfBGA). This high-density package was one of the fastest growing new products in the company’s history.
Then there’s Intel, where the first enterprise-class system-on-a-chip (SoC) product developed. This SoC integrates several key system components into a single-architecture-based processor. The 2008 Tolapai product is expected to reduce chip sizes by up to 45% and power consumption by 20% compared to a standard four-chip design, while improving throughput performance and processor efficiency. The Intel CE 2110 media processor, an SoC architecture for CE devices, is designed to help manufacturers accelerate time-to-market for smarter, cost-effective designs. CE-optimized IA-based SoC will be introduced in 2008.
Tessera’s MicroPILR platform may become a building block of next-generation mobile, computing, and consumer electronic products, especially in high-density, package-stacking applications. This 8-die flash package stack, less than 1.2-mm thick, can be tested prior to stacking. It could help the industry achieve greater levels of integration and functionality at lower cost.
If there’s a way to save on costs, those building newer-style packages seem to find it. Materials suppliers – Rohm and Haas Electronic Materials, Henkel, Rogers Corp., and others – all support specialty materials and chemistries for dealing with emerging packages for providing stability, thermal control, protection, and attachment. SiP RF technology design is being offered by Cadence as a method for designing in reliability. Equipment suppliers are able to meet and adapt to thinner wafers through specialized support and handling devices. Throughout the supply chain, the importance of new packaging styles is recognized.
Gartner predicts that the semiconductor assembly and test services (SATS) market will grow another 6.2% in 2007, due in part to integrated device manufacturers (IDMs) and OEMS expanding adoption of outsourcing business models, and continued transition to advanced packages. Overall industry revenue totaled $19B in 2006. Prismark also supplies a rosy picture ahead, estimating the interconnect market will grow from approximately $34B in 2006 to $51B in 2011.
It’s great to be involved in an industry so poised for growth, and so sexy.