Renesas hints at new CPU architecture for MCUs

May 21, 2007 – Renesas Technology Corp. says it is developing a new CPU architecture to provide “revolutionary” enhancements to 16- and 32-bit microcontrollers in terms of code efficiency, processing performance, and power consumption. The company won’t reveal specifics of the architecture until early next year, though, and the new CPUs aren’t expected to hit the market until mid-2009.

Benchmarks of the new as-yet unnamed 16/32-bit CISC architecture, based on Renesas’ 90nm flash MCU process, include a list of improvements:

– Twice the performance in terms of MIPS/MHz
– 5x higher operating frequency (up to 200MHz
– 30% reduced code size
– 50% less power consumption (<0.05MA/MHz dissipation)
– Larger flash memory (up to 4MB of on-chip flash)
– Cost advantages of 300mm/90nm-and-below manufacturing nodes.

The devices also will be compatible with the company’s existing M16C, R32C, and H8 lines, and complement (but not be compatible with) 32bit SuperH RISC devices. Products to incorporate the new CPUs range from PCs and networks to consumer electronics and industrial applications. CPUs for automotive electronics will be released later depending on market demand, Renesas noted.

“We are developing next-generation CPUs for 16- and 32-bit markets under a single architecture, in response to the growing demand for both 16- and 32-bit MCU products,” said Hideharu Takebe, board director and general manager, MCU business group, Renesas Technology Corp., in a statement.

A white paper with more in-depth background, descriptions, and all kinds of charts about anticipated benefits can be found at


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