by Bob Haavind, Editorial Director, Solid State Technology
At least six months can be lopped off time-to-market for new chips through co-development and concurrent qualification efforts, stated Scott Jewler, EVP and chief strategy officer for Singapore’s STATS ChipPac, at a ConFab panel on packaging called “Think Outside the Fab.”
Jewler identified key time slots where concurrent work must take place in order to achieve reduced cycle times. At the foundry, appropriate technologies must be harnessed right along with the chip designers’ efforts to clearly understand market needs. In the next time slot, when a commercially viable chip is being visualized, it is necessary to identify needed fab processes including the back-end-of-line (BEOL) design. Then it’s time to mobilize manufacturing facilities and process modules and do qualifications of both front-end and BEOL process steps. As this is achieved, production can be ramped into high-volume manufacturing.
Next comes joint delivery and fulfillment of orders while maintaining yield and services and delivering product to packaging/assembly/test BEOL operations. Sometimes early orders for 40,000 parts in a product that “hits” can grow quickly to million-per-month levels.
This concurrent approach has proven to cut at least six months from the time-to-market from fab to back end, according to Jewler. During the Q&A session, he explained that skilled test designers can develop much more efficient test programs than typically come from chip design firms. But the need for this specialized work fluctuates too much, so there is no good business model to have a group like this available. — B.H.