SST May 2007: FujiFilm Microdevices achieves a means of tweaking CCD sensitivity

EXECUTIVE OVERVIEW This month’s edition of Chip Forensics by analyst Dick James delves into the manufacturing of a charged-coupled device (CCD) sensor for a FujiFilm digital camera with ISO 3200 sensitivity and 1/2000th sec shutter speed. He finds that the CCD, although a relatively simple structure in this nanotech era, is nicely optimized to do exactly what is required in a 6Mpixel camera.

One of the fastest growing consumer product segments over the last few years has been the DSC. Digital sales exceeded film camera sales a couple of years ago, and a number of manufacturers have now stopped film camera production entirely. In 2004, DSC sales were $77 million, and were projected to be ~$100 million in 2006, according to Mizuho Securities. Of course, those figures are eclipsed by camera-phone sales, but that is arguably a different market.

Within the DSC market, there is a split in imaging technology between the two types of image sensors: CCDs and CMOS imagers. CMOS technology is taking over the lower-cost end, while CCDs still dominate the high end, although not exclusively. Canon has a number of higher-end models using CMOS imagers, including the EOS 5D, which uses a 12.8Mpixel full-frame (24 × 36mm) CMOS sensor.

For this installment of Chip Forensics, we chose a CCD sensor from a FujiFilm Finepix F30 6.3Mpixel camera, which uses its proprietary Super CCD design. For a point-and-shoot camera, it has impressive resolution as well as ISO 3200 sensitivity and 1/2000th sec shutter speed. Recently, Gear Digest dubbed it the world’s best point-and-shoot (“Is FujiFilm’s FinePix F30 the best point-and-shoot?” Barry Gerber, January 31, 2007).

The sensor in this camera is very similar to one we analyzed a year ago ( FujiFilm’s Finepix E550, which is also a 6.3Mpixel camera, but with an ISO rating of only 800. The latter used the fourth generation of the Super CCD, whereas the F30 uses the sixth generation design.

The FujiFilm MS3897A described here is a Super CCD HR VI, the 2006 version of the technology originally announced in 1999, with the pixel size reduced to 2.7µm sq. to improve resolution. In its Sendai, Japan, fab FujiFilm Microdevices manufactured the chip using a 0.35µm, two-metal, double-polysilicon process, using p-wells in an n-substrate. The die size is 7.7 × 9.0mm (69.3mm sq.).

The Super CCD design rotates the conventional x-y array 45° to align the pixels diagonally, optimizing real estate with comparatively larger octagonal photodiodes and allowing closer spacing. Fujifilm claims “a balanced combination of resolution, sensitivity, dynamic range, signal/noise ratio, and color fidelity” as a result of this layout.

Figure 1. Cross-section of CCD pixels. (Source: Chipworks)
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A cross-section of the structure (Fig. 1) is oriented diagonally across the die so we can see the details of the pixel in its laid-out orientation. The organic hemispherical lenses are at the top, followed by a color filter layer over an organic planarizing layer. Below that are silicon nitride lenses, and below those are the photodiode and CCD charge transfer electrodes. (Our sample-preparation has separated the two nitride layers in the lower lenses.)

Figure 2. Top view of nitride lenses. (Source: Chipworks)
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Figure 2 is a plan-view image of the chip with the organic layers removed and the nitride lenses exposed, clearly showing the diagonal layout of the pixels.

Figure 3. Close-up of pixel structure. (Source: Chipworks)
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Figure 3 zooms in on the silicon structure, again showing where the two nitride layers—the lower deposited over the CCD structure and then planarized, and the upper deposited on the planarized layer—are formed into an almost spherical shape. The two polysilicon transfer electrodes (etched out by our silicon stain) below are covered with a tungsten (W) light shield.

The stain has shown some of the doping in the substrate; the lighter spots between the electrodes are the n-doped charge transfer channels, surrounded by p-isolation diffusions. The lighter surface regions separating the pairs of electrodes are the p-pinning layer at the surface of the photodiodes, which are visible below, between the p-isolation regions.

Figure 4. SCM cross-section of pixel doping. (Source: Chipworks)
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The scanning capacitance microscope (SCM) cross-sectional image in Fig. 4 more clearly illustrates the substrate doping. Starting at the bottom, the yellow region is the n-buried layer in the n-substrate, graduating into the array p-well; the upper yellow areas are the photodiodes; the dark purple regions at the substrate surface are the p-isolations between the photodiodes, and the p-pinning layer at the surface of the diodes; and finally, the light spots in the p-isolation are the n-doped charge transfer channels. Above the surface, the transfer electrodes and dielectrics appear as blank areas, covered by the tungsten light shields.

Figure 5. Polysilicon electrodes and pixel apertures. (Source: Chipworks)
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Returning to plan-view, Fig. 5 is an image of the array polished to show the polysilicon transfer electrodes running horizontally across the array; the line immediately below the diamond-shaped apertures is the poly 1 layer. In two of the apertures, there is some residual tungsten, defining the roughly rhombic (not octagonal, as FujiFilm claims) light access to the photodiodes. The zig-zag pattern of the control lines enables the readout of red, green, and blue pixels on every horizontal line. This is a significant advantage over conventional CCD design in which horizontal lines are occupied by either red-green or blue-green pixel pairs. To produce RGB color signals in a conventional CCD, two consecutive lines must be read.

Figure 6. Plan-view SCM image of pixel doping at substrate surface. (Source: Chipworks)
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Figure 6 is a plan-view SCM image of the silicon surface of the pixel array. We can see the zig-zag n-doped transfer channels surrounding the faint diamonds of the p-pinning layers within the blue p-isolation areas in the pixels. The pink strip running diagonally across the pixel is an artifact caused by a slight recess at the edge of the poly-1 gate (see Fig. 3), which allows the SCM probe tip to scan slightly deeper into the substrate.

Using the charge transfer channel, the collected charge is clocked out of each photodiode by the transfer electrodes to the edge of the CCD array, where a secondary CCD transfers the charge to the first-stage amplifier, and thence to the signal processing circuitry.

When we compared this chip to the sensor from the Finepix E550 that we had analyzed earlier, we found that the pixel array was almost exactly the same. The pixel size was the same at 2.7µm on a side; the aperture fill factor was slightly larger at 14% (vs 12%); the structure looked similar; and even the final 69mm sq. chip size was the same. Thus, there is presumably no additional amplification circuitry to give the enhanced ISO 3200 sensitivity.

Figure 7. Comparative images of first-stage amplifiers in Finepix F30 and E550 CCDs. (Source: Chipworks)
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The clue came when we looked at the first-stage amplifiers of the two parts. Both the E550 and the F30 appear to have the same eight-transistor amplifier (Fig. 7), but on closer inspection, the transfer gates (T1) from the secondary CCD are different. The images have different color casts since there were different color filters on our different samples.

Figure 8. Comparative images of transfer gates (T1) and reset transistors. (Source: Chipworks)
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Figure 8 shows close-up images of the transfer gates and reset transistors with insets of even higher magnification. In these optical images we cannot really see much, but if we squint hard we could think that the F30 transistor is slightly shorter and wider. As an aside, we can see some process differences—multiple vias and dummy structures are used in the newer part.

Figure 9. Cross-sectional images of transfer gates. (Source: Chipworks)
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The cross-sectional images in Fig. 9 illustrate that the F30 transistor not only is shorter, but also has a different profile, indicating that it was formed from the Poly 1 layer, whereas the E550 device was defined in the Poly 2 layer. The actual transistor dimensions, as best as we could measure, were 0.8µm long × 1.5µm wide for the F30, with a ~24nm gate oxide; and 1.1µm long × 1.4µm wide, with a ~40nm oxide for the E550. There may be other parametric differences such as diffused resistances (n+ diffusions in the F30 are deeper, at ~0.2 vs. 0.14µm) that could also affect the amplifier gain, but we have not investigated to that degree of detail.

So it appears that the change in size of this single transistor, coupled with some process enhancements, has allowed the sensitivity of the image sensor to be improved from ISO 800 to ISO 3200. The CCD itself is a relatively simple structure in this nanotech era, but nicely optimized to do exactly what is required in a 6Mpixel camera. Not bad for a camera that sells for less than $300.

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DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected],


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