May 2, 2007 – STMicroelectronics says it is sampling 65nm multi-interface physical layer interface IP for low-power SoC devices, supporting 3-6Gbps Serial ATA hard disk drives.

Physical layer macro-cells perform the high-speed serialization and de-serialization of data to and from the drive and provide a 20-bit-wide parallel interface to the link layer, the company explained, in a statement.

The company says the new 65nm PHY IP achieves 35% reduced die sizes and 30% reduced power over previous-generation 90nm IP. Also, improvements in equalization and transmitter and receiver circuitry result in enhanced jitter tolerance and lower transmit jitter, according to ST.

ST is planning to integrate blocks from its portfolio of 65nm IP, including this MoPHY IP, into next-generation 65nm SoCs.