June 2007 Exclusive Feature 2: 3D INTERCONNECTS
IITC PREVIEW: Are 3D interconnects ready for prime time?

By Phil LoPiccolo, Editor-in-Chief

Among the most significant developments in interconnect slated to appear at this month’s International Interconnect Technology Conference (IITC, June 4-6, in Burlingame, CA) involve 3D chip architectures. Sitaram Arkalgud, director of SEMATECH’s interconnect division and its newly created 3D interconnect initiative, calls 3D chip architecture his “new religion,” because stacked chips allow interconnects to be much shorter than in traditional 2D configurations. This technique, he claims, could be the most promising route to reducing resistance-capacitance (RC) delays, the main stumbling block to higher chip speeds and lower power consumption.

Traditional approaches to reducing RC delays face serious obstacles. For instance, lowering the relative permittivity (k value) of the dielectric materials surrounding metal interconnect lines, in order to reduce the signal-retarding capacitive coupling that occurs when the lines are placed closely together, has progressed more slowly than the International Technology Roadmap for Semiconductors (ITRS) timetable has specified, explained Arkalgud, and that trend could continue. At the 32nm node, the ITRS calls for keff to be between 2.1-2.4, he noted. The problem is that lowering the k value, typically by adding porosity, means the mechanical properties of the materials (hardness, elastic modulus, etc.) all go in the wrong direction, and damage resulting from etch, ash, and CMP processes needs to be eliminated. Also, the use of low-k support layers (etch stop, caps, hard masks) is essential to realize the low-keff value). Consequently, expensive new tools, such as low-downforce CMP, must be integrated into process flow to compensate for the more fragile materials.

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