June 19, 2007 – Fujitsu Ltd. and Fujitsu Laboratories Ltd. say they have developed 45nm LSI logic chips, combining low-power consumption and high-performance interconnect technologies.
The 45nm process incorporates high-temperature millisecond annealing to form shallow source/drain regions to reduce leakage current by up to 80% vs. previous levels.
The company also uses a low-k nanoclustering silica (NCS) in a lower interconnect region, which was already added to Fujitsu’s 65nm process but is now being used between different layers to further reduce interconnect capacitance. The low-k NCS (k=2.25) — “the lowest of any insulating film reported to date,” according to Fujitsu — reduces interconnect lag time by 14% vs. standard 45nm interconnect technologies.
Fujitsu aims to have the 45nm process ready sometime in 2008 to incorporate into LSIs for mobile devices.
(above) Cross-section of 9Cu + 1Al interconnect module with Full-NCS at lower Cu layers.
(below) Relation between source/drain junction depth and leak current.