June 19, 2007 – Klaus Schruefer, chief scientist for Infineon’s multigate FET technology project, tells WaferNEWS why mugFETs are being pushed out beyond 32nm, and what’s highest on the to-do list to get the technology ready for chip manufacturing, even by the 22nm node.
Infineon extends multigate-FET work
In an interview with WaferNEWS, Klaus Schruefer, chief scientist for Infineon’s multigate FET technology project, confirmed that the latest info from the company seems to push mugFETs out beyond the 32nm node, whereas in discussions back in December around IEDM there was talk that only 45nm would be too early. “What has changed in the meantime is progress on high-k and metal gates,” he said. “Of course, each and every company wants to stay planar as long as they can, if it’s possible.”
Asked what are the challenges Infineon faces to get the promising mugFET technology ready for production, he indicated there are a range of issues from a manufacturing, equipment, and design standpoint — though yields and reliability of the manufacturing process are not a concern.
One of the hurdles to multigate FETs has been integration with design. FinFETs are totally different structures, requiring new computer models built with data from actual results on silicon, which implies months or years of running processes. Schruefer acknowledged that compact modeling remains “an open question” and probably won’t be ready until mid- or late-2008. However, he added that he saw “really good progress” on compact modeling at this year’s VLSI Symposium, in papers presented by the U. of California-Berkeley on its “BSIM” model (Berkeley short-channel insulated-gate FET), and NXP’s work on its “PSP” model is “following very fast,” he noted.
A bigger concern is getting metrology technology to catch up with these new chip architectures. To have multigate finFETS ready for 32nm or even 22nm chip manufacturing, that means the metrology needs to be ready 18-24 months from now, Schruefer explained. And right now, for example, there’s no “mature” technology to measure plasma doping concentration on the sidewalls of a 3D device. Consortia including IMEC and SEMATECH are working on these metrology issues (e.g., atomic-force microscopy for vertical measurement of doping densities, and other things like line-edge roughness SEMs for fins), but Schruefer admitted that progress is “too slow.” “Metrology has to be ready when you start to really develop the technology,” he said. “We hope that things will be ready when we need it.” — J.M.