June 13, 2007 – Infineon has disclosed an update to its work with multigate transistors, saying it’s completed tests of circuits made with the new transistor architecture on 65nm processes, incorporating more than 23,000 transistors that incorporate “all of the key components” in current circuits plus SRAM. The device’s record 13.9 picosecond switching time is 40% better than the previous version, touted at December’s IEDM.

“We have measured a quiescent current that is a factor [of] 10 lower than in today’s integrated circuits,” which doubles energy efficiency and battery life of mobile devices, according to Hermann Eul, head of Infineon’s communication solutions business group. “These efforts give us high confidence that the integration of multi-gate transistors combined with our leading know how about applications will result in cost-effective solutions and power sensitive applications.”

Infineon reiterated its position from IEDM 2006, that although the transistor architecture has been created using 65nm process technologies, it will likely not be used in mass production until at the 32nm node, partly in connection with work being done at partner IMEC.

Last December, in an exclusive interview with SST and WaferNEWS, Klaus Schruefer, principal scientist for CMOS devices of Infineon Technologies, explained that for 45nm low-standby power (LSTP) digital circuits, finFETs provide equivalent performance to 45nm “planar” transistors with 1/10th the leakage current, the costs of manufacturing are nearly identical (within 2%-3% in terms of overall process complexity — e.g., the use of raised source/drain regions, selective epitaxy, and complex STI), and the chips should consume one-half the battery power.