June 15, 2007 – Renesas Technology Corp. is reporting improved results for its high-performance transistor technology with “low-cost fabrication capability” for 45nm-and-below microprocessors and SoC devices, utilizing the company’s complimentary metal insulator semiconductor (CMIS) hybrid structure first disclosed at IEDM in December 2006.
The technology incorporates titanium nitride metal and polysilicon gates, as well as some implant and etching process tweaks, that can be produced economically starting at the 45nm node without major changes to existing fabrication processes. The device also utilizes strained-silicon manufacturing techniques to boost current drive capability, since the hybrid structure “closely resembles the transistors of a CMOS process,” Renesas noted.
The prototype 40nm-gate-length devices Renesas discussed at IEDM had transistor drive performance of 620 µA/µm (n-type) and 360 µA/µm (p-type). The newer 40nm prototypes disclosed at this week’s VLSI Symposium have drive capacity of 1068 µA/µm (n-type) and 555 µA/µm (p-type) at a 1.2 V power supply voltage, producing about a 20% performance improvement compared with the previous structure.
The technology has a p-type transistor with a titanium nitride (TiN) metal gate (a 2-layer structure instead of single-layer gate, for better threshold voltage), and an n-type transistor with conventional polysilicon gate. The p-type transistor gate stack is as follows: high-k, CVD-TiN, PVD-TiN, and polysilicon. Silicon diffusion into the CVD TiN layer from the polysilicon electrode is suppressed (because the PVD-TiN layer is more dense than the CVD TiN layer), preventing property changes that would otherwise increase the threshold voltage. Also, the two TiN layers lower the transistor’s threshold voltage by ~100mV, to a level appropriate to a low-leakage device, Renesas claimed.