Renesas tips 32nm on-chip SOI SRAM

June 15, 2007 – Renesas Technology Corp. has developed a technology for implementing SRAM in 32nm processes and beyond for on-chip SRAM incorporated into a microprocessor or SoC.

The technology uses silicon-on-insulator (SOI) to individually control substrate parts of the three kinds of transistors composing SRAM, thus “greatly extend[ing]” the SRAM operating margins, the company explained in a statement.

The technology also incorporates a partially depleted SOI MOSFET to apply the body potential, and a hybrid trench isolation structure with both full trench isolation that completely eliminates the SOI layer, and partial trench isolation that enables the body voltage to be controlled by allowing a thin SOI layer to remain under an isolating oxide film, making it possible to apply a different body potential to each transistor, Renesas explained.

The company says it has built and evaluated 2Mb SRAMs using 65nm CMOS processes using this technology, resulting ~100mV improvement in operating lower-limit voltage, plus 16% better read margins (static noise margin), 20% write margins, and a ~19% reduction in transistor electrical characteristic variations. In 32nm and 22nm simulations, static noise margins were seen to improve by ~27% and 29%, respectively.

IMAGE: Micrograph of a SOI SRAM test chip.


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