TI: We’ll use high-k for 45nm after all

June 13, 2007 – Texas Instruments has turned the tables on plans for its 45nm process technology, now saying that it will in fact incorporate a hafnium-based (HfSiON) high-k dielectric material for its future high-performance 45nm chips.

“We’re confident that our high-k choice overcomes the technological hurdles faced through continued digital CMOS scaling and the transition to smaller process geometries,” said Hans Stork, TI’s CTO, in a statement.

The high-k dielectric is made by CVD-depositing HfSiO which is then reacted with a downstream nitrogen plasma, TI explained, adding that incorporating high-k will reduce leakage by >30x per unit area vs. SiO2 dielectrics.

TI reiterated its original timeline for ramping the 45nm process, starting with its first 45nm product (a wireless chip) to be sampled later this year followed by qualified production by mid-2008. TI also is creating a 45nm midrange process for DSPs and an ASIC library for communications infrastructure products.

The first 45nm recipe to incorporate the high-k dielectric will be a high-performance version for MPU-class performance, but TI only said vaguely that this high-k flavor will be introduced “in later versions” of the 45nm process.

A year ago, TI a href=”http://sst.pennnet.com/articles/article_display.cfm?Section=ARCHI&C=TETAK&ARTICLE_ID=257500″>tipped details of its early 45nm process, using immersion litho and an ultralow-k dielectric (k=2.5) to reduce interconnect capacitance by 10%, as well as incorporating the company’s first use of silicon germanium in its strain techniques. But TI said it wanted to avoid integration of new and complex high-k materials, by exploring techniques such as full-silicidation-of-polysilicon (FuSI), or a combination of metal plus a silicide, to utilize a dual work function metal gate “at some point” in its 45nm technology roadmap.


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