June 12, 2007 – Presenting at the VLSI Symposium this week in Japan, Toshiba says it has developed a new 3D memory cell array structure using “through-holes” that could be a potential candidate for higher-density NAND flash devices.
The new structure (see images, above) incorporates pillars of stacked memory elements that pass vertically through multistacked layers of electrode material, and which share peripheral circuits. The device increases cell density and data capacity with minimal increase in die size and using current process technology, according to the company.
The process involves driving through-holes down through a stacked substrate of gate electrodes and insulator films; filling the holes with pillars of lightly-doped silicon; and the gate electrode wraps around the silicon pillars at even intervals (see image, below). A preformed nitride film with a SONOS structure (silicon-oxide-nitride-oxide- silicon) is set in each joint, functioning as a NAND cell. The electrical charge is held in the silicon-nitride film formed inside the gate holes, and traps are formed to lock the electrical charge inside.
The new array increases density without increasing chip dimension, according to Toshiba, which claims a 32-layer stack has 10x the integration of a standard chip formed with the same process technology generation. The company says it will further develop the technology to improve security and reliability.
Other groups are also working on SONOS as a future memory device technology. Last fall, Samsung said it built a 32Gbit/40nm device with a pseudo-SONOS flash memory structure dubbed “charge trap flash”. Earlier this week, US and Korean researchers said they have fabricated a hybrid memory device incorporating both silicon nanowires and nonvolatile (SONOS) technology. And Taiwan’s Macronix is also said to be working on SONOS, though development work is expected to continue for several more years.