June 4, 2007 – TSMC has released its reference flow 8.0 supporting the foundry’s process technologies down to 45nm (and up to 0.25-micron), including statistical timing analysis for intra-die variation, automated DFM hot-spot fixing, and new dynamic low-power design methodologies.
“TSMC’s 45nm process technology requires ever-deeper collaborations with EDA vendors and other partners in our design ecosystem,” and so is built to provide “a seamless link between the designers and advanced process technologies,” said Kuo Wu, deputy director of design service marketing at TSMC, in a statement.
The 8.0 reference flow incorporates improvements in DFM methodology including automated DFM hot spot fixing, DFM electrical variability consideration, increased automation, and integrated analysis and optimization capabilities. The flow also incorporates power reduction techniques including TSMC’s “adaptive voltage scaling” to help reduce active power consumption in next-generation mobile devices. It supports the Silicon Integration Initiative’s (Si2) Common Power Format (CPF), which was developed and donated to Si2 by Cadence. For statistical analysis, the 8.0 reference flow builds on interdie statistical timing analysis available with TSMC’s 7.0 version by adding statistical leakage and statistical timing optimization.
In related news, TSMC has launched what it calls an “active accuracy assurance initiative,” a design-based program to provide accuracy standards for all stages of design and manufacturing for all TSMC partners, including EDA vendors, IP providers, and library developers.
Under the initiative, TSMC’s manufacturing data is data-mined and results shared with EDA vendors and other partners to develop their own methodology. “The initiative provides assurance to designers that they can maximize the performance of their designs without having to compensate or ‘guard band’ for unforeseen variations in the manufacturing process,” said Wu, in a separate statement.