UMC, ARM build 65nm SOI test chip

June 4, 2007 – ARM says it has created a test chip incorporating physical IP (libraries for standard cell and I/O, plus single-port SRAM memory compiler) using UMC’s 65nm process technology and silicon-on-insulator (SOI) technology.

The L65SOI process features nominal 1V multi-threshold voltage thin gate oxide transistors, nominal 2.5V thick gate oxide transistors for I/O, and a nominal 1V 0.62 sq. micron 6-transistor SRAM bitcell, according to the companies. The ARM standard cells used in the test chip support multi-VT and multi-power supply circuit designs, with a 3.3V signal-tolerant I/O and memory compiler optimized for high-speed and low-power consumption. A full process design kit is now in place and ready for use.

Initial circuit analysis indicates that the design saves up to 20% in area and 30% in power consumption, compared to a part produced to reach the same performance on bulk CMOS at 65nm, the companies note. Using SOI also offers up to 28% speed boost with 10% power reduction over bulk CMOS.

Tom Lantzsch, ARM’s VP of marketing for physical IP, said in a statement that the new process through UMC “will enable leading fabless design companies to assess SOI technology and begin pilot projects,” adding that the next step will be extending to more advanced process nodes and adding a full foundry program similar to what it offers in bulk CMOS.


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