Big push coming on two routes to 3D

by Bob Haavind, Editorial Director, Solid State Technology

3D chip packaging with through-silicon vias (TSV) will sweep across the industry over the next 3-5 years, based on presentations and discussions at SEMICON West. Using TSVs will enable very compact packaging offering much better performance. Many chipmaker roadmaps include 3D as an interim step from the 45nm to the 32nm node, sources said.

There are two main routes to this 3D future, according to consultant Neil Moskowitz of Chip Connections Consulting Inc., at a SEMATECH-organized session. One is based on current system-in-package (SiP) multichip modules but without the wire bonding. The second is a fab-like approach — and thus more complex — using wafer-to-wafer, die-to-wafer, or die-to-die bonding. Both eliminate wire bonding.

The first approach lends itself to memory chips, Moskowitz explained. Samsung, for example, laser-drills holes through pads to make contacts. Conductive inks between regular rows and columns provide internal traces. Vertical Circuits Inc. uses printed traces on the edge of stacks as well, he said. Pad extensions can be used with suitable isolation.

The fab-like approach allows heterogeneous chip stacks with a goal of exceeding 10,000 I/O per die to improve device electrical performance, according to Moskowitz. An Intel microprocessor would now require 10,000 bumps, he explained — roughly 9000 for power and ground, and 1000 for other signals. This is becoming too dense for today’s chip-scale packaging. Going 3D will also improve electrical performance. Fab processes take a lot of non-recurring engineering (NRE) costs, he explained, because of chip diversity. The cost has limited this approach to premium applications, such as edge servers and medical devices. There is great appeal, though, for much wider application, eliminating the need to put microprocessors, SRAMs, and other functions that require different processes onto the same chip. He sees very compact circuit cubes in the future, in spite of many hurdles that remain to achieve this form factor, including testing problems, a lack of infrastructure, and potential thermal problems.

Moskowitz sees the evolution coming in three phases. Phase I will include developments such as Samsung’s H stack and multilayer ICs, such as flash memory, at the wafer level. Conductive pastes may be used in some cases.

Phase II involves surface-to-surface bonding. This would offer big performance gains for applications such as cell phones. Compressible bumps don’t have to be of uniform height, and gold bumps don’t require flux. Surface bump pitches might eventually reach 5-microns, he said.

Phase III is a move to system-on-silicon, Moskowitz said. A microprocessor die, for example, might have face-down chips bonded to it for memory, graphics, and other functions. One approach would be to put vias through a passive silicon interposer chip, with active circuit chips face down on either side. Cooling fluid might run through microchannels in the interposer. He sees this approach being used 3-5 years from now as the pressure builds to move from 45nm to 32nm. The ability of a small multidie package to act like a single die will make the 3D circuit cube approach very appealing.

While wafer-to-wafer bonding might promise cost advantages, the problem will be with bad die on one wafer or the other. This approach might work best for flash, Moskowitz suggested, due to redundancy. Flash die with only 5% good cells can theoretically be used for wafer stacking, because the flash controller can “skip” the bad cells, he explained. In die-to-die bonding, few die will be done as direct flip-chip, he said. It is more likely that a redistribution layer would add bumps to a regular die.

Sharath Hosali of SEMATECH said that his group has development cost models for 3D approaches. Each chipmaker has its own roadmap for TSVs, he said, and they are all very product-specific. Wafer-to-wafer bonding will be for high-end chips only, where all die on both wafers are the same size and yield is very high.

Chip-to-wafer bonding allows varying chip size, and there is a tradeoff between alignment time and accuracy. Vias may be put in before or after processing, but the via-last approach may require drilling through 8-9 layers of interconnect, which could be a big problem. Approaches will include face-to-face, face-to-back, or back-to-face methods.

Hosali described a wide variety of techniques being explored to make vias (etch in parallel or laser-drilled serially up to 10-microns deep), passivate and line the holes, metallize, bond, thin, and dice wafers. Vias might be drilled on the front side and the wafer thinned until they come through the back.

Toolmakers are already developing tools suitable for the coming 3D era. Lam Research, for example, is using its experience in etching deep trenches and MEMS devices to offer a via-etch tool. It could adopt the techniques developed to both 200mm and 300mm etch equipment, according to Jackie Seto, managing director, software, MEMS, and packaging. A slightly tapered, very smooth sidewall, will be required. One advantage of the TSV wafer-to-wafer approach is that the chips on each wafer can be smaller, so yield could be high even with a few defective chips. While chipmakers have TSV on their roadmaps, most haven’t worked out integration schemes yet, according to Seto.

A consortium has already formed in the industry for developing a 3D packaging infrastructure, and research funding is steadily increasing. — B.H.


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