PACKAGING BEAT: SEMICON West Preview: More assembly and test than ever

by Jeff Demmin, Contributing Editor, WaferNews

As usual, the challenge for SEMICON West attendees is prioritizing among the many options to make the best use of your time. SEMICON West seems to have more “extras” than ever, and this year many of them are focused on assembly and test.

With the next biennial update to the International Technology Roadmap for Semiconductors (ITRS) due in December, Wednesday’s (July 17) Summer Public Conference for the 2007 ITRS will be a good opportunity to get information from the current drafts of each working group — and they still welcome public feedback, too. Updates typically highlight changes from the previous edition, and looking at these changes is a great way to see what the experts think is either more or less important or challenging than two years ago. A very full agenda covers every chapter in the ITRS, and a panel discussion titled “More than Moore” should cover some topics related to the 3D technology that is helping to address the conventional scaling described by Moore’s Law.

One of the more efficient options is the half-day Kulicke & Soffa Interconnect Symposium on Tuesday afternoon (July 17), which promises a view of advanced packaging from all possible angles, from the analyst community to a major chip company, a large subcontractor, and a materials/equipment supplier. Jan Vardaman, president of TechSearch International, will offer an update on “Advanced Packaging Interconnect Trends and Technology.” Recent focus areas for TechSearch have included developments in Asia and materials trends, and those are certainly big topics now. Freescale scientist Stephen Lee will give an update on wire bonding on Cu / low-k devices with bond pads on top of active circuitry. Challenges with Cu / low-k have been studied for years, but “bond over active circuitry” is an important space-saving approach that can decrease the die size. Flynn Carson of STATS ChipPAC will talk about “Advanced 3D packaging and interconnect schemes,” which covers perhaps the most critical areas in packaging today. K&S VP Robert Chylak concludes the session with a talk on ultrafine pitch copper wire bonding.

A series of technical sessions held under the “Test, Assembly, and Packaging TechXPOT” umbrella also promise some interesting updates. The sessions include advanced packaging trends and packaging material trends, as well as three separate sessions on various aspects of test. Joint sponsors of these sessions include MEPTEC, IMAPS, and FSA, which should contribute to fresh content with a variety of viewpoints.

Perhaps the most interesting trend in the TAP TechXPOT is the quantity of test coverage. A session on “Critical issues in test” includes speakers from Advantest, Credence, Verigy, Teradyne, and Qualcomm, scheduled to discuss topics including “Redefining the value of test in an era of commoditization” — a particularly important topic for the industry given the escalating cost of test. Another test related session, “Best of Burn-In & Test Sockets and IEEE Semiconductor Wafer Test workshops,” has selected presentations from the events, as well as an overview presentation by Jerry Broz, general chair of the IEEE event.

Last but not least, on Thursday (July 19) representatives from throughout the supply chain, including Intel, LogicVision, TSMC, and ASE, give their views on test as “A gating factor for success at advanced nodes.” A key concept to be discussed is the need to reduce the cycle time for test and debug. Faster cycle times improve the test quality while decreasing the time to market, which all contributes to a higher value-added for the test process. As usual, it all comes back to cost, which is why SEMI is focusing on test so much in 2007. — J.D.


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