IMEC looks to the future as SEMICON West opens

by Debra Vogler, senior technical editor

As another SEMICON West opens, IMEC’s experts — coming off a round of paper presentations at the VLSI Symposium — discussed what they see as being key to the future of semiconductor industry.

New markets to explore. Luc Van den hove, EVP and COO of IMEC, believes that it won’t just be traditional scaling that will drive the industry. “The CMOS processes currently used in manufacturing for logic and/or DRAM show the promise of a whole new future industry driver,” he told WaferNEWS. Referring to the development of new devices and systems, such as integrated smart sensors, power devices, CMOS MEMS and NEMS devices, biochips, etc., he noted that, while process scaling R&D is mainly driven by DRAM, processor, and advanced logic applications, these smart devices and systems can be developed using a CMOS baseline process integrating sensor and actuator functions, or modified for optimized power handling capacity, operation voltages and drive currents, or using above IC thin-film technology for integrated passives and MEMS. Aside from customer demand, he believes innovation and creativity will be the major drivers. “Key for these developments will be the combination of an increasingly wider set of expertise, ranging from CMOS process and design technology, over packaging and interconnect technologies to the bio-nano convergence domain. We will see plenty of opportunities and new markets to explore.”

Bringing FinFETs to manufacturing. Serge Biesemans, department director, CMOS device and technology research at IMEC, believes that FinFETs are a promising approach to address short-channel effects and leakage as CMOS is scaled to the 32nm node and beyond. Because the ultra-thin body FinFETs that IMEC has been researching need no channel doping, it is anticipated that concerns with doping fluctuations in nano-scale planar devices can be addressed using this new transistor structure. “This [new structure] results in reduced parametric spread due to dopant fluctuations together with reduced junction leakage,” he said.

While Biesemans notes that the FinFET structure allows for the implementation of a function with less logic gates than a conventional structure, he does allow that there are still some manufacturing bottlenecks that will have to be overcome. However, at the recent VLSI Symposium, IMEC presented data showing that SRAM cells and data path demonstrators with low standby current and good low operating power performance were realized.

Stacking the deck. Referring to 3D integration as the Holy Grail for system integration, scientific director for interconnect, packaging, and systems integration at IMEC, Eric Beyne, hailed the technology — in which different IC layers are vertically stacked — as having a lot of potential. He cited applications such as memory, portable device, and high-performance computers, to heterogeneous integration of biotech with nanotech, and processing power. But as with almost every new technology, some hurdles will have to be overcome. “To fully exploit the potential of these novel 3D technologies and limit the integration cost, developments have to start from a product perspective,” he told WaferNEWS. “Actual system requirements such as cost, testability, functionality and power have to be taken into account. Also, system architectures need to be revised and design tools need to be upgraded to enable 3D optimization across heterogeneous technologies. Both the technology and the design methodologies developments need to be tightly coupled.”

Deposition challenges hit up low-k at advanced nodes. Rudi Cartuyvels, department director for interconnect, packaging, and systems integration at IMEC, told WaferNEWS that gaining early insight into the metallization challenges of sub-32nm (16-32nm) technologies will require test vehicles of narrow trenches. “Good filling can already be achieved down to ~40nm width,” he said. “Surface and phonon scattering of the electrons are the main contributors to the wire resistivity.” He noted that the filling of trenches thinner than 40nm becomes more challenging and will require a better control of the deposition of the barrier and copper seed at the sidewall. — D.V.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.