IMEC updates 32nm litho progress

July 16, 2007 – At SEMICON West, European R&D consortium IMEC is disclosing it results after a year of 32nm half-pitch work, noting progress in all three of its areas of focus: high-index 193nm immersion litho, double-patterning, and EU.

“We’ve made significant progress in the three litho approaches we are investigating within our advanced lithography program,” said Luc Van den hove, EVP and COO at IMEC, in a statement.

IMEC says it will switch out its current litho tool, an ASML XT:1700i (1.2NA) tool, with the company’s new XT:1900i (NA=1.35) tool in its 300mm cleanroom sometime in 2008. Several fluids are being investigated to jack the index up to the NA=1.55-1.60 required to push 193nm to the 32nm half-pitch node, and IMEC says at least one fluid “seems to meet most criteria in terms of lithographic and interaction properties.”

IMEC also says that, using an in-house critical dimension CD uniformity (CDU) model, it has demonstrated potential capability to achieve sub-3nm CDU, showing that a more uniform wafer CD distribution can be achieved by minimizing the mean difference between the CD populations, compensating for intra-field CD variation, and optimizing the etch variation across the wafer (see image, above).

The consortium is also looking at techniques to automate the split full chip designs, another production requirement, and with EDA partners is currently investigating constraints to ensure designs are split compliant. And a resist freezing process flow (see image, below) that skips the intermediate etch step, by treating the first litho pattern so that the second resist layer can be coated and patterned on top of it, “shows promising results,” according to IMEC.

“We are quite confident that double patterning will be taken up as an intermediate solution for 32nm half pitch before a single exposure solution is ready for production,” stated Van den hove.

Meanwhile, looking at EUV, IMEC says it has entered the last phase of integrating ASML’s alpha demo tool with a Sn source, involving fine-tuning the optics for high-resolution imaging and acceptance testing. Research so far has focused on interference exposures for resist preparation (work done at the Paul Scherrer Institute in Switzerland), design and reticle tape-out, and on EUV simulations to prepare all the projects.


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