by Debra Vogler, senior technical editor
A few weeks ago, before the bustle of SEMICON West, Silterra announced an extension of its JDP with IMEC to create a foundry-compatible 90nm CMOS process technology, with the intent to further scale to 65nm. A 110nm derivative will also be developed in parallel. A 130nm process, the fruit of a previous joint effort, is already in production at Silterra. WaferNEWS caught up with Silterra president and COO, Tzu Yin Chiu, to get the latest on the foundry’s plans.
“Our goal is to have the 110nm node, which is a cost-reduction version of the 130nm process, ready for pilot production by mid-2008,” said Chiu. “It will be followed by the 90nm process in the second half of the year and the 65nm technology a couple of years after that.”
At the present time, the foundry sees the sweet spot for its business at the nodes between 180nm and 130nm, although Chiu added that customers are starting to shift to the more advanced nodes.
When asked to consider the possibility that the industry’s drive to consolidate will start hitting the smaller foundries, Chiu predicted that there will be winners in the second tier as well. “The winners will be those with the right customer set, the ability to follow technology, and who can provide a complete IP offering,” said Chiu. “The smaller foundries will look for partners with complementary strengths.”
WaferNEWS also caught up with IMEC’s VP of business development, Ludo Deferm, about the competitive landscape that foundries large and small will face going forward. Deferm believes that the smaller foundries will have to make strategic alliances with either smaller IDMs or with the large foundries, where they can offer capabilities that the larger foundries do not want to offer. “Going forward