by Fran&#231oise von Trapp, managing editor, Advanced Packaging

At Wednesday’s (July 18) Packaging Materials Trends TechXPOT, sponsored by IMAPS, industry experts shared insights and developments in packaging materials and applications, and how innovations will help device packaging address functionality, form factor, and reliability challenges.

Gregg Rudd, chief technologist at Spectra-MAT Inc., pointed to materials innovations at the wafer level with lithography-grade controlled expansive substrates. These substrates are made of a composite material that boasts a conductivity approaching that of aluminum, and improved thermal conductivity over other substrate materials, such as ceramics. Large flat wafers are fabricated as thin as 150 &#181m. Future product development will involve tightening specifications, improving wafer surface finish, and adding functionality through lithographically patterning the wafer, he said.

Rick Lathrop, application manager at Heraeus, contact materials division, described a method of BGA coplanarity reduction, contending that by intentionally varying solder paste aperture size, BGA packagers can reduce coplanarity. The process involves screen printing solder paste using a stencil with different-sized apertures to compensate for the different ball sizes, he explained. Findings show that the unique warpage topology needs to be well understood prior to implementation. Thicker stencils are required, as well as fine powder pastes. Smaller starting ball diameters amplify the effect, while smaller under bump metallization (UBM) diameters with equal solder volume can increase ball height.

Continuing the screen printing advancements discussion, Rita Mohanty of Speedline Technologies talked about an alternative solution to sphere placement for second-level interconnect assembly, or package-to-board interconnect. According to Mohanty, conventional sphere-attach systems are expensive and reaching process limitations. Vibrating the stencil at the time of stencil-substrate separation pushes the limits of conventional stencil printing below the 0.66 area ratio. This enhanced print technology could produce higher bump heights, slightly higher overall yields, and better bump coplanarity. Enhanced solder paste stencil printing can be an attractive, cost-effective solution, she concluded.

Joe Fjelstad, CEO and co-founder of SiliconPipe and Advanced Packaging advisory board member, spoke about how IC packaging has played a pivotal role since its origins, and continues to hold the key to electronics in the future. The need for speed and miniaturization is driving 3D technology and high frequencies approaching the multi-GHz range, and 3D packaging is one solution, Fjelstad noted. “The advantage of stacking is that we’re maximizing the amount of silicon to get more performance,” he explained. He outlined challenges with high power and increased frequencies, then identified an interconnect gap between what the IC can do and what the PCB can support. “Traditional chip-based solutions are running out of steam,” he noted. Silicon, package, and PCB all need engineering consideration concurrently, and design tools are evolving to address this.

Rounding out the session, Henkel’s Michael Todd, another Advanced Packaging advisory board member, reported on the company’s low-warpage mold compound development. Alain Coulombe, president and CEO of SolVision, talked about the company’s answer to 3D technology for wafer inspection, which was a 2007 Technology Innovation Showcase (TIS) award winner at SEMICON West. — F.v.T.