by M. David Levenson, Editor-In-Chief, Microlithography World
The main topics for discussion at Applied Materials’ press event at SEMICON West on Tuesday (July 17) were about high-k/metal gate processes (HK+MG) and double patterning lithography, though much of the talks concentrated on the gate technology. Still, the self-aligned double patterning results described in a handout seemed really impressive. To make a 22nm half-pitch structure, Applied first printed 22nm lines at 88nm pitch in APF using an immersion stepper at Albany Nanotech, according to Kenneth MacWilliams, VP and GM of the Mayden Technology Center. Then they deposited 22nm of nitride on the APF and removed the sacrificial APF structure. The result was a 22nm half-pitch nitride that could be etched into the substrate (see Fig.1 above). Ultimately that method could be used on a complex TANOS flash memory gate stack at 32nm (see Fig.2, below).
Complicated gate stacks will be used in the next generation of flash memory as well as for future logic. The ability to etch perpendicular walls in all the complex films — without footing or undercutting — will be key to making future generation technologies work. The complex multi-chamber cluster tools introduced at the Applied lunch can now do that, at very small dimension.
To emphasize the lunchtime event’s theme that “The transistor is cool again,” the centerpiece of every table was a foot-square cube of clear ice, with the topic and Applied logo printed on two sides in porous white ice. Verlyn Fischer, senior product marketing manager, etch products business group, suggested that a damascene process was used to make them. First the cube of clear glass was frozen out of de-aerated water and then trenches forming the logo and lettering were milled into the very-cold crystal. Those trenches were then filled with carbonated water that froze as bubbly white ice, and then capped with a thin layer of slowly frozen air-free water. A final CMP-like polish insured optical quality surfaces. — M.D.L.