by Debra Vogler, senior technical editor

SEMATECH is continuing to discuss many of the themes from papers it presented at the VLSI Symposium (see our previous reports on the VLSI Symposium by SST editorial board member John Borland: Part 1 and Part 2). According to Raj Jammy, director of front end processes at SEMATECH, the consortia has settled on a gate first/high-k metal-inserted poly stack (MIPS) electrode approach instead of FUSI or replacement gates. “We’ve been doing high-k/metal gate [research] for quite a while and we chose a path that was more manufacturable and that fits in more easily with existing technologies in terms of scalability, contamination prevention, and integration,” said Jammy, in a pre-show interview with WaferNEWS.

Noting that FUSI hasn’t played a role in recent announcements from IC manufacturers, Jammy told WaferNEWS that it has a long way to go until it is manufacturable. “Replacement gate is an option; a couple of companies have pursued it,” he said, though he noted that scalability of this approach is also a big issue.

SEMATECH continues to remain mum about exactly which materials systems are preferred for pFET metals — details are reserved for consortia members, but Jammy did say that three or four solutions have been discussed. For nFET metals, two candidate systems within the lanthanide series have been identified, but which of these is the best is, again, only available to member companies.

Along with materials selection, annealing is another “hot” topic at SEMICON West. Jammy noted that at 45nm, some companies will use millisecond annealing (flash or laser), though some may only need spike annealing at this node. By 32nm, however, he projects that almost everyone will have to use millisecond annealing, with the possibility that some applications may need a combination of the two anneals. — D.V.