Cadence, ClearShape execs hint at future DFM integration

August 21, 2007 – Execs from Cadence Design Systems and Clear Shape Technologies talked about their proposed M&A deal with WaferNEWS and Microlithography World, hinting that integration will soon go deeper than just an interface, and what other applications besides litho are in the pipeline.

Terms of the deal, which closed Aug. 15, were not disclosed. All 35 Clear Shape employees have joined Cadence’s products and technology group.

Clear Shape’s technology — which many in the industry point to as the best example of an actual design-side DFM tool — improves the ability to detect lithographic ‘hot spots,’ as well as model the impact of optical processing variations on the electrical performance of the chip, the companies explained, in a statement.

The meat of the acquisition will be integrating Clear Shape’s predictive (and manufacturing/OPC/tool independent) lithography capabilities into the Cadence DFM environment. After working together for more than a year the firms have achieved a “first level of integration” with interfaces between Clear Shape and Cadence’s Encounter and custom platforms, and now “we see opportunities for something deeper than an interface,” suggested Mike McAweeney, Cadence’s VP DFM marketing. He wouldn’t say more, instead indicating that details of a deeper integration will be discussed at the company’s CDNLive user group meeting in a few weeks.

McAweeney added that customer demand to make the companies’ technologies work more closely together ultimately drove the M&A deal. “Customers have always said that individual tools aren’t important, but integration of those tools into the flow is,” he said.

Tackling lithographic effects early in the design phase is an increasingly important factor in getting 65nm and below chip designs ramped to production, noted Richard Brashears, corporate VP of manufacturing, modeling and implementation at Cadence. Previously, designers were forced to put “way too much margin into their designs” to account for possible variations in what eventually gets onto silicon, “or take the risk because they don’t have good visibility,” he said.

“No matter how much OPC you apply, you’ll never get exactly what you model in the layout — silicon always is different, and you need to predict and account for that,” added Atul Sharan.

Atul specified that one of Clear Shape’s benefits of working with various OPC tools (e.g. Invarium, or ones from Synopsys or Mentor Graphics) will continue to be a feature even as the companies weave Clear Shape’s technology into Cadence’s platform. “Ultimately foundries make that choice anyway [of what OPC tool to use],” Atul noted.

He also pointed out that lithography is a big, but only one component of Clear Shape’s technology application, in addition to other targets like CMP variation, and strained silicon which is something that’s “coming down the pipe,” he said.

InShape uses a nonlinear optical transformation algorithm to detect potential manufacturing failures during physical design to predict full-chip contour shape predictions across the process window (see figure). Using output from InShape, OutPerform takes timing, and place/route data together with encrypted fab technology files to identify timing and leakage parametric hotspots for violations due to systematic variations. The resulting timing optimization directive drives place/route tools.

Clear Shape has been working with TSMC, UMC, IBM, Samsung, Chartered, NEC, and others to correlate its contour predictions to a specific fab’s silicon (i.e., calibrating the models), and has achieved contour prediction calibration and hot spot detection for several customers, including TSMC (65-55-45nm), the IBM/Chartered/Samsung alliance (65nm), and NEC (90-65nm). STARC also is a recent customer.


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