By John Borland, contributing editor, Solid State Technology

The VLSI Symposium meeting this year (June 12–14, Kyoto, Japan) revealed there will be not one, but many different solutions for the production implementation of hafnium-based oxides at the 45nm node and beyond, with Hf-based dielectric k values varying from a “medium”-k (8–12) up to a true high k of 22–24. The gate electrode for some companies will remain poly, while others will use a very thin metal/thick poly stacked layer (metal inserted polystack, “MIPS”) and others will use a metal-only electrode. If metal is used, it can be single metal, or dual metal for nMOS and pMOS.

Various gate process flow integration approaches will also be used: gate-first; gate-first, but with disposable spacer (reverse source drain); gate-last (replacement gate); and a hybrid of gate-first for one type of MOS transistor, and gate-last for the other type of MOS transistor. The question is, how long can the industry support these multiple approaches? Some technologist say they must converge by the sub-32nm node, while others feel it may never converge.

Handicapping the HK+MG field
Technologists from Intel, NEC, IBM, Toshiba, Samsung, and SEMATECH participating in an evening panel discussed the status and prognosis for high-k/metal gate (HK+MG) transistors, suggesting that there will be many different solutions for high k with kvalues varying from 8–24 in combination with gate electrodes including poly only, poly/metal stack, or pure metal