TSMC approves 300mm WLP packaging plan, 0.18-micron upgrade

August 15, 2007 – TSMC board members have given their approval to a pair of proposals targeting capacity investments for 300mm wafer-level packaging and an upgrade to its 200mm/0.18-micron logic process.

The first item is a $59.8 million capital appropriation to establish 300mm wafer-level packaging technology and capacity, which the company says will reduce the size of its end products and make it (and its customers) more competitive in the market.

The Taiwan Economic News reported that the packaging investments are in preparation for work on AMD’s Fusion microprocessor which has integrated graphics capabilities, and for which multichip packaging and wafer-level packaging methods would reduce production costs and manufacturing risks. TSMC has been the major foundry source for AMD’s graphics chips since the chipmaker absorbed ATI Technologies last year, the paper noted.

TSMC is slated to begin volume production of AMD’s “R670” graphics chip and its “RD790” chipset later this month, using 55nm and 65nm process technologies, respectively, the paper reported, adding that the two products are a big reason behind TSMC’s strained 300mm capacity.

The other spending plan involves $22.8 million to upgrade its 200mm output using 0.18-micron logic process to be capable of high-voltage radio frequency (RF) and BiCMOS processes. The actual monthly capacity for the process, though, will be reduced by about 12% to 11,100 200mm wafers/month.

TSMC had been rumored to be looking at expanding in-house testing and packaging services, targeting 65nm flip-chip testing and packaging in 2007 followed by 45nm in 2008, partly through an expanded partnership with Advanced Semiconductor Engineering (ASE).


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