WCJTG report: Spike RTA+ms annealing could delay introduction of complex metal gates

by Debra Vogler, Senior Technical Editor, Solid State Technology

Applied Materials’ Susan Felch reported results of experiments done in conjunction with NXP Semiconductors, IMEC, and Matsushita Electric Industrial Co., at the recent West Coast Junction Technology Group meeting (July 19 in San Francisco). She showed data that indicated a spike rapid thermal anneal (RTA) followed by a millisecond laser anneal improves polysilicon gate depletion to the extent that it opens up the possibility of being able to delay the introduction of complex metal gates until the 32nm node for most applications.

After first performing RTA, the researchers used a medium-power laser (temperature=1200°C) to perform millisecond annealing. Using this process flow, Felch reported a reduction of 1.4&Aring in the polysilicon gate depletion (T inv ) for PMOS transistors, while the T inv reduction for NMOS transistors was 1.5&Aring (see image below. [T inv is the combination of dielectric thickness plus the equivalent thickness of the depleted capacitor in the poly-Si near the dielectric (the two are basically capacitors in series).]

“When using a metal gate, the object is to reduce the poly depletion thickness down to 0 [i.e., reduce the T inv thickness to just the thickness of the dielectric itself],” said Felch. “So reducing the thickness of the overall capacitor by 1.4Å is a big step moving in that direction…this should help to delay the introduction of metal gates.”

Also notable was the finding by this particular group is that a medium-power laser anneal gave much better overall results for NMOS and PMOS devices than using a high-power laser anneal (1300°C). For NMOS devices, there was an 8% improvement in device characteristics using a medium-power laser vs. only a ~4% improvement using a high-power laser. For PMOS, there was a 2% improvement using a medium-power laser but no improvement using a high-power laser. By investigating a thermo-mechanical stress model of the gate dielectric interface (SiON) during laser anneal, the researchers attributed the difference in results obtained between medium- and high-powered lasers to induced interface traps that break bonds at the interface of the dielectric. These induced traps, the result of stresses arising because of the difference in thermal expansion coefficients between the polysilicon and the silicon, generate fixed charges in the dielectric (SiON).

Event co-chair John Borland, founder/president of J.O.B. Technologies, told WaferNEWS that other groups have not seen a degradation in gate oxide or other performance deterioration when using spike RTA first followed by millisecond annealing — in fact, there have been mixed results depending on the group and applications. For example, he cited research at AMD/Dresden (reported at the Electrochemical Society’s May 2007 meeting) in which there was no gate oxide degradation when spike anneal was performed first, followed by millisecond annealing for 65nm volume production. Mattson Technology (at INSIGHTS, 5/07) has also reported that flash lamp anneal (FLA) first followed by spike anneal results in deeper junctions than if spike anneal is done first, and the then followed by FLA. — D.V.

For more on annealing, click here to watch SST on the Scene videocast with John Borland.

(Image source: Applied Materials)


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