September 11, 2007 – Cadence Design Systems and Stratosphere Solutions are collaborating to increase 45nm semiconductor device yields by targeting manufacturing variability, combining their technologies to offer improved process modeling, analysis, and implementation flows.
The pact combines Cadence’s Encounter digital IC design platform with Stratosphere’s Ozone variability modeling environment, to support an end-to-end flow from parametric yield measurement, modeling and characterization to design analysis, optimization and final signoff, the firms said. The result is a comprehensive methodology for 45nm design that minimizes impact of potential systematic (lithography, chemical mechanical polishing) and random variations.
The combination helps users “analyze impact of within-die, die-to-die, systematic and random variation on design,” in order to “significantly mitigate [the] impact of process variation, improve performance predictability, and prevent silicon failures,” explained Prashant Maniar, co-founder and chief strategy officer of Stratosphere, in a statement.
Foundries and semiconductor companies using Stratosphere’s parametric yield metrology platform “produce massive amounts of fab data that can be translated into accurate statistical models,” noted Mike McAweeney, VP of DFM marketing at Cadence. “Our collaboration with Stratosphere has produced a comprehensive and seamless flow that helps customers to prevent, analyze and optimize for manufacturing effects and manage process variation.”