by Dr. Paula Doe, Contributing Editor
Deep etching equipment is about to make a big jump in throughput, according to Franz Laermer, corporate sector research and advanced engineering at Robert Bosch GmbH, and inventor of the widely used Bosch process for deep reactive ion etching. These faster volume production speeds will not only bring down the costs of MEMS devices to expand their use in consumer applications and wafer-level packaging, but will also make production of 3D interconnect with through-silicon vias practical, he told SST partner Nikkei Microdevices.
Laermer reports in NMD‘s July issue that recent improvements to the basic Bosch process significantly improve its throughput, and major tool suppliers now developing it further are on track to have 100µm/min etching tools on the market within two to three years.
The relatively slow speed of etching out deep features remains a bottleneck for cost-effective high-volume production. Typical DRIE tools may get throughput of 10-25µm/min, depending on the exposed area, which is sufficient for automotive devices, but still limiting for things like consumer sensors and semiconductors. Very recently producers’ roadmap deep etch target for 2010 was only 50µm/min, but now both consumer MEMS makers and chipmakers are demanding higher throughput. 3D interconnect processes are especially limited, often able to etch through-silicon vias at the impractical rate of only a few wafers/hr. With the IC etch market potentially far larger than the MEMS market, tool suppliers are putting resources into developing higher throughput tools to meet that market’s needs.
Key to improving throughput is increasing the energy input without increasing the disturbances in the plasma that result in uneven etching, and minimizing the passivation time between etch cycles. The Bosch process etches down vertically by alternating etching and passivation, bombarding the silicon with high energy plasma to carve out a hole, then coating the hole with a layer of Teflon-like polymer film to protect the sidewalls from further erosion before the next round of etching. Researchers have now increased the voltage feed to 5kW, but introduce the high frequency voltage to both ends of the coil that induces the plasma instead of just one, producing a more symmetrical plasma. An added delay line shifts the phase of one end by 180°, so each end cancels out the uneven flow patterns generated by the other. This simple approach limits the usual capacitive coupling, taming the electrical fields in the plasma that produce displacement currents and uneven plasma density, which result in uneven etching. A magnetic field is also added within the chamber to further align the plasma shower so it hits the wafer vertically, for more uniform etching at high power.
The process uses the usual SF6 etchant and C4F8 passivation gases, but delivers them at 10Pa high pressure so they hit the wafer at higher speed, 1000cm3/min at atmospheric pressure. The passivation phase is cut to 100-200ms for 1-2 sec of etching, using a pump that emits etchant gas by default, with a valve that switches over for quick bursts of passivation gas as needed. — P.D.