October 8, 2007 – A group of 19 chipmakers, designers, tool suppliers, and research partners are forming a new industry group to expand and accelerate usage of silicon-on-insulator (SOI) by touting the technology’s performance and power consumption benefits to a wider audience of end users.

In general, the consortium will focus on achieving three major goals: addressing users’ needs, collaboration in the ecosystem to enable silicon-proven solutions, and promoting SOI benefits, technology innovation, and ultimately momentum in the greater electronics community. Specifically, the group’s initial tasks will be sharing best practices by early adopters and facilitating new design proof points about SOI’s performance, power, and area advantages.

Andre-Jacques Auberton-Herve, chairman of the SOI Industry Consortium (and top exec at SOI supplier Soitec), laid out the consortium’s three-committee structure, governed by a nine-member board that will be appointed later this month, and elected annually. A SOI user committee will explore customer priorities and end-user advocacy, while a technology enablement committee will work with the design community, demonstrating silicon and custom & digital design flows and “proof points” for consumer, multimedia, and mobile designs. A marketing committee will craft educational treatises touting “SOI’s benefits to users,” and will be responsible for increasing consortium membership, facilitating dialog about SOI out in the industry, and explore new segments for SOI adoption.

In a phone interview after the Webcast presentation, Auberton-Herve acknowledged that the consortium’s focus will be to find out what end users need, and to push SOI’s benefits to them in terms of performance and power consumption — and that initially these discussions will come before issues about the cost of SOI (e.g. vs. high-k and metal gates [HK +MG]), which eventually “will be addressed” as a part of finding a “cost-effective solution” for end users, he explained to WaferNEWS. “There will be some [end-user’s] roadmaps with some tradeoffs, some benefits, and some benchmarking,” he said. “Cost is part of it, but it’s more to see how SOI benefits [end-users] globally in performance and power consumptions. These are the key elements in pushing SOI.” For users planning out their strategy for the 32nm and 22nm nodes, that may indeed involve both SOI or HK+MG or even both, he noted, pointing out that “all the tweaks in the engineering bags will be needed.”

Of the three committees and their to-do lists, the technology committee likely has the most to do up-front, Auberton-Herve noted. Key elements to work on understanding customers’ priorities and provide guidance and benchmarking, as well as enable design flows, IP availability, and share best practices. “We need to make [those] known quite soon,” he said, though he didn’t provide a timeline.

Founding members of the SOI Industry Consortium include: AMD, ARM, Cadence Design Systems, CEA-Leti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, NXP, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Synopsys, TSMC, and UMC. In his presentation, Auberton-Herve suggested membership could expand to 60 members from “all components of the ecosystem,” but that the timing of this announcement was meant to showcase “those who have shown key energy and momentum” for SOI adoption and success.