IMEC eyes MIMCAP work for scaling DRAM to sub-50nm

October 15, 2007 – IMEC has launched a research effort into DRAM metal-insulator-metal capacitor (MIMCAP) process technology to address the material and integration requirements to scale DRAM MIMCAP to 50nm and beyond technology nodes.

Scaling DRAM to and beyond the 50nm node, will require MIMCAP dielectrics with a higher dielectric constant, such as ZrO2 — that means an effective oxide thickness of 0.5nm by the sub-50nm node in mid-2008, and to 0.3nm in 2009 for the sub-45nm node. Scaling the dielectric equivalent oxide thickness while attaining very low leakage currents is currently a bottleneck in scaling DRAM, and addressing this challenge is part of the plan for IMEC’s CMOS device scaling program, IMEC noted in a statement.

The first part of the work, part of IMEC’s sub-32nm CMOS device scaling program, aims to set up a baseline process for MIMCAP evaluation, based on TiN electrode and a ZrO2 capacitor dielectric, for screening new electrode materials such as W, Mo, TaC, Ru, and others. A second phase will screen new material stacks combining high-k and electrodes for potential integration, using the ITRS‘s DRAM specifications as selection criteria — e.g., leakage current <1fA/cell, and <20nm total physical MIM thickness.

Thirdly, a MIMCAP deposition process will be developed with an eye toward major integration issues, mimicking as much as possible the effect of full DRAM integration such as passivation, anneal, etc. MIMCAP test structures will be integrated and characterized on electrical and reliability performance. Both MOCVD and ALD will be used since they allow depositing high-quality thin films, according to IMEC.


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