IMEC, GaTech seeking help for 32nm packaging interconnect work

October 15, 2007 – IMEC and Georgia Tech’s Microsystems Packaging Research Center (PRC) say they want more help to research next-generation flip-chip and substrates to address “IC-to-package-to-board” packaging interconnect issues for ICs at the 32nm node and beyond.

The two groups are setting up an industrial affiliation program to explore, develop, and invent new solutions to interconnect high-density ICs with very tight I/O pitches (down to 40-20µm peripheral) to low-cost packages and printed circuit boards, targeting novel packaging approaches to reduce the mechanical stress on the IC after packaging and assembly — packaging techniques that “become indispensable” with Cu/low-k on-chip interconnections, the groups say in a statement.

The two-year program will target technologies to solve four major barriers to next-gen flip-chip packaging of scaled ICs and ultralow-k dielectric ICs:

Organic package interposer substrates that minimize stress at die and package level, and enhance the wiring density, fine I/O pitch routing capability, and high-frequency signal performance of substrates;
– New fine-pitch flip-chip under-bump metallization and barrier metallization technologies that meet the electromigration and thermo-mechanical reliability targets of flip-chip scaling;
– Novel solder and non-solder interconnect approaches, including advanced underfill materials and processes, to meet future current density, geometry, and reliability requirements; and
Thermo-mechanical modeling, design, and verification for improved reliability.

“We are excited to start this unique open program with PRC where we intend to bring together 20-30 expert researchers from industry and academia worldwide,” said Eric Beyne, IMEC’s program director for interconnect, packaging and systems integration. “Only by joining expertise and know-how from leading players in the packaging and semiconductor field, we will be able to realize highly reliable solutions beyond the traditional flip-chip

Prof. Rao Tummala, Director of Georgia Tech’s PRC, added that PRC and IMEC offer “synergy in expertise and facilities in ICs, packages and systems” that will be “critical to address the barriers in flip-chip reliability, electromigration, ultra-fine pitch I/O substrates and IC-package interconnections.”


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