Mask industry survey: Steady as she goes, no icebergs ahead

by M. David Levenson, Editor in Chief, Microlithography World

The photomask industry is puttering along as usual, according to the 2007 annual industry self-assessment survey presented by Gil Sheldon at the SPIE Symposium on Photomask Technology (Sept. 18). Revenues maintained their recent 1.2% of the global semiconductor industry (to $3.1 billion), and the number of plates shipped has held steady at 700,000/year as it has for 25 years. Higher average selling prices of more advanced reticles are driving sales, with 61% of income generated by plates intended for ≤180nm production, which constitutes only 22% of volume. Toppan Photomasks and DPI are the top two merchant manufacturers (23% and 20% marketshare, respectively), but captive masks shops are estimated to produce 35% of the total. Oddly, more than half the masks produced are intended for 5X magnification, and the great majority are binary and lack OPC embellishment. Except for phase-shifting masks, yields remain comfortably above 90%. About 40% of masks require no repair, and a nearly equal number are repaired using laser tools, with more sophisticated technology applied to the rest. Data volume is growing more rapidly than expected and 193nm pellicles are degrading more rapidly than others, but none of the industry trends appears especially threatening, according to the survey.

Almost all of the papers discussed at BACUS dealt with refinements of technology supporting optical lithography, with EUV and imprint notably under-represented. Since the exposure wavelength will stay at 193nm and water immersion can only raise the numerical aperture to 1.35, the practical limits of conventional imaging (at k1=0.3) are quite visible (CDmin =k1 λ /NA= 43nm). Even approaching them requires designs to take optical limitations into account through DfM methodologies and aggressive resolution enhancement technologies (RET). Successful implementation of DfM and RET strategies requires detailed understanding of processes — including mask manufacturing processes such as e-beam exposure and mask etching.

Apo Selzinger of Cadence presented a study that showed how systematic CD errors appeared during the chromium etch step of att-PSM fabrication and were then propagated through manufacturing. He advocated an OPC-like correction scheme in which polygon edges were moved to account for etch nonlocalities, rather than the more conventional e-beam dose modulation. However, such a scheme would interfere with today’s wafer OPC models and rules, possibly causing a properly fabricated mask to negatively impact yield.

Another surprise was the result of early measurements of phase-shift on circuit dimension features of att-PSMs done with the Zeiss Phame mask measurement tool. Ute Buttgereit showed that measurements of the true optical phase shift depended both on the incident illumination angle and the mask feature, with isolated att-PSM lines showing much larger phase errors than tight gratings under realistic off-axis illumination conditions. Such an imaging induced error could limit the utility of this popular technology. However, another paper from Freescale indicated that the att-PSM specs need not be made tighter for advanced nodes.

A remarkable portion of the meeting was devoted to reticle technologies that would transcend the conventional single-resist exposure limit though multiple patterning technology, in which several optical exposures into different resist films together pattern a single circuit layer. Such a strategy facilitates new RET schemes that would be totally prohibited with previous single resist layer methods, such as the use of printing assist features (PrAF) in one exposure that are erased in a subsequent one. Henning Haffner of Infineon showed how such schemes can reduce the mask error enhancement factor and loosen the specs that maskmakers must hit for 32nm circuits. Proper PrAF insertion reduced across-chip and across-device linewidth variation as well as line-end retrenchment. The challenge is to decompose layouts and insert PrAFs appropriately. — M.D.L.

Next week, WaferNEWS will report on the consensus at BACUS that double patterning technology may be utilized for the next half-pitch node or two, and why the evident delay in EUV technology poses special challenges for the photomask community.

Image source: Shelden Consulting (data from Gartner Dataquest)


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