October 15, 2007 – The Open NAND Flash Interface (ONFI) coalition of memory suppliers, formed in mid-2006 to develop a chip-level standard interface for NAND flash memory, has added another specification — a block abstraction to simplify host controller design.
In most NAND flash memory products, the driver in the host controller must recognize complex physical-=address defining each physical memory array to the block and to the byte of data, and changes in device architecture require modification to the driver, complicating system upgrades, the group notes. Adding block abstraction (BA)allows the host to treat the flash as a pool of addressable blocks of data, instead of managing them individually. New flash components based on the BA NAND flash specification can incorporate traditional NAND-specific functions such as error-correcting code (ECC), wear-leveling, and bad block management in the internal memory controller, freeing the host of these tasks, the group claims.
Back in January ONFI delivered its 1.0 spec, which defined NAND device behavior such as command and register sets, pin-out, electrical parameters and packaging, and incorporated a “self-describe capability” to expand the range of NAND flash components that can be accommodated, and enable support for new flash components with minimal software changes. A second-generation ONFI specification currently under development will add high-speed performance to the BA capabilities.
The ONFI group was founded in May 2006 by Hynix, Intel, Micron, Sony, Phison, and STMicroelectronics, boasting nearly 40 members. Still a notable omission, however, is memory giant Samsung, which has supported other memory industry standards groups such as JEDEC, MIPI, and MMCA. The ONFI Q&A page still claims that Samsung “supports the objectives of the ONFI initiative,” and that the group is working with the company to resolve some concerns on a few items in the ONFI legal agreements.