Intel product launch event yields more insight into its manufacturing strategy

by Debra Vogler, Senior Technical Editor, Solid State Technology

Intel’s Research Day in June provided information about the company’s proprietary pixelated mask technology, a technology that was not needed for either the 65nm or 45nm node. At that time [June], it appeared that this mask technology would not be required at 32nm, but it would be ready for 22nm in case EUV and double-patterning are not. At this week’s celebrated launch of 17 new Intel products, all based on 45nm node technology (including high-k/metal gate), a few clues emerged as to what’s next on the company’s lithography roadmap. However, it is still not clear if the pixelated mask technology will be used by the company at 32nm.

What is clear is that Intel will be using immersion lithography at 32nm. “We may insert EUV at 22nm…if the tools are ready and they’re more cost-effective,” said William Holt, SVP & GM of Intel’s technology and manufacturing group, in a conversation with WaferNEWS during the event. “We don’t think they’ll [tools] be ready — at least on our schedule so, we’re looking beyond 22nm at this point. We may insert EUV at 22nm if in fact it comes along when our manufacturing is going online and it in fact provides us a cost benefit.”

Though not willing to make a firm prediction about EUV, Holt acknowledged that Intel remains convinced there is a place for it and the company will continue to keep the momentum going by funding further development both internally (e.g., mask technology) and externally. “We want this capability available because we don’t want it to be a limiter that has everybody slowing down


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