NEC details 40nm eDRAMs

November 19, 2007 – NEC Electronics and its US and German subsidiaries have debuted two versions of 40nm system-on-chip devices with embedded DRAM, incorporating the same high-k dielectric features in its 55nm devices developed last fall.

The UX8GD technology boasts clock speeds up to 800MHz and low operating power; the UX8LD eDRAM has low leakage-current levels to reduce power consumption by up to two-thirds vs. equivalent SRAM. Cell sizes are 0.06 sq. microns, 50% smaller than the previous 55nm versions, with 50% reduced overall chip size.

The 40nm process include specific process technologies from NEC’s 55nm process unveiled last fall, including high-k dielectric materials (including hafnium gate dielectrics, nickel-silicide gate electrodes, and zirconium-oxide DRAM capacitors), which lower impurities and resistance in the channels, resulting in lower leakage current between the drain and source, longer-term data storage, fewer variations in transistor performance, and greater performance of both logic and memory, the company explains, in a statement.

Shipments of 55nm eDRAM samples began last month, with plans to ramp to volume production by the end of the current fiscal year (March 2008). Volume production of the 40nm devices is slated to start at the end of the next fiscal year (March 2009) at NEC’s 300mm line in Yamagata.


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