November 12, 2007 — 3D Interconnect Program, the first supplier in the group launched in 2005 to evolve traditional copper/low-k interconnect technology to 3D chip stacking.
The two already had been working together to jointly address early development challenges in 3D through-silicon vias (TSVs), including deep-silicon reactive ion etching (DRIE), cost modeling, process benchmarking, standards development, and technology roadmapping, and the company’s contributions in front-end and back-end processing and MEMS “has proven invaluable to these efforts,” noted Sitaram Arkalgud, program director, in a statement.
The promise of 3D-TSV technology, which requires bonding semiconductor wafers and dies using deep TSVs for interconnects, is that it will provide cost-effective ways to integrate diverse CMOS technologies, and eventually link CMOS chips with emerging technologies such as MEMS and biochips.
The goal of SEMATECH’s program is to enable high-volume manufacturing of 3D-TSV chips by its members with an optimum combination of cost, functionality, performance, and power consumption.
“3D integration will be a key driver of semiconductor density, performance, functionality, and productivity,” said Arkalgud. “To realize the full potential of 3D, “we will need the collaboration of a broader cross-section of industry participants. TEL’s investment in our program is a major step in that direction.”