BY WARREN W. FLACK AND HA-AI NGUYEN, Ultratech, Inc.,
ELLIOTT CAPSUTO AND CRAIG McEWEN, Shin-Etsu MicroSi, Inc.
Copper pillar bumps were introduced in 2006 by Intel in their 65-nm “Yonah” microprocessor. Wafer bump foundries and semiconductor manufacturers are actively evaluating this new technology. Integration of photolithography and electroplating is critical to the fabrication process.
As pin counts and interconnect densities increase, interest grows in copper pillar bumps as an alternative to conventional solder bumps for flip chip and wafer-level packaging.
Copper pillars offer advantages over solder bumps such as higher interconnect densities, higher reliability, improved electrical and thermal performance, and reduction or elimination of lead. While solder bumps collapse during solder reflow, copper pillars retain their shape in the x, y, and z directions (Figure 1). This allows for fabrication of finer bump pitches, smaller passivation openings, and finer redistribution wiring for higher interconnect densities.
Figure 1. Comparison of conventional solder bump (left) and copper pillar (right).
The fabrication of thick copper pillar structures requires close integration of the photolithography and electroplating processes. A thick photoresist layer acts as a mold for copper electroplating. The material must be capable of coating, exposing, developing, electroplating, and stripping with conventional equipment and standard ancillary process chemicals. In addition, photoresist sensitivity and process bake and development times are critical to minimize cost-of-ownership of the lithography cell. For the electroplating process, the photoresist profile, plating durability, and stripability after plating are important considerations. Furthermore, the choice of a positive resist is important to obtain the process advantages of a dark field mask.
Copper Pillar Fabrication
Arrays of copper pillars were fabricated on 200-mm Cu seed wafers at various diameters and pitches. A chemically amplified, positive photoresist with high contrast and resolution* was selected for the mold because of its exposure speed, line-edge profile, and ability to achieve high transparencies for thick-resist processing. The photoresist was coated to a thickness of 55 µm in a single application using standard wafer-track processes. However, the coater needed to be configured with a high-viscosity pump and large-diameter tubing to facilitate dispensing of thick photoresist, which can have viscosities in the range of 5000 mPa·s. Immersion development time was 7 minutes using 2.38% TMAH at room temperature. No post-exposure bake or delay time between exposure and develop was required.
Figure 2. Cross sectional SEMs of typical 15-μm (left) and 50-μm (right) square contacts in photoresist.
The photoresist was exposed on a 1× stepper based on the 1× Wynne-Dyson lens design with a 0.16 numerical aperture and Mercury ghi-line illumination from 350 to 450 nm.* The low NA and broadband illumination spectrum of the stepper provides a large depth of focus and minimizes the standing wave pattern in the resist side wall near the substrate. The exposure dose and focus offsets of the stepper were optimized for 50-µm contacts in the photoresist. A wafer-edge exposure (WEE) system was used to create a photoresist-free area around the edge of the wafer for electroplating.
Figure 3. Cross-sectional SEMs of 50-μm square contacts in photoresist at -30-μm focus (left) and +5-μm focus (right).
The 200-mm wafers were copper electroplated using an automated, high-performance single-wafer system.* The electroplating target height was 35 ±5 µm. After electroplating, the photoresist was easily stripped in acetone.
The lithography process linearity was determined by measuring grouped contact arrays from 15 to 100 µm and fitting the data to a line. The process was highly linear with a small photomask bias of -0.27 µm. The small reticle bias helps simplify reticle design and fabrication for the copper pillar process.
Figure 2 shows cross sections of typical square photoresist contacts in a dense contact array on a copper seed substrate. Contacts as small as 15 μm are resolved in a 55-μm thick photoresist film, with straight sidewalls and minimal rounding at the top of the photoresist. There is a small foot at the base of the photoresist in features sizes below 20 μm. However, the observed footing had minimal impact on the copper electroplating structure. The observed resolution exceeds the 50-μm contact size for copper pillars currently being considered for advanced packaging applications. This resolution margin provides enhanced critical dimension control and process latitude for a production lithography process.
Large-focus latitude is an advantage in controlling photoresist critical dimension over local topography variations. The focus latitude of the photoresist was evaluated using 50-μm contacts in a dense contact array on a copper seed substrate. Figure 3a shows that at -30-μm focus offset, there is some rounding at the top of the photoresist, while Figure 3b shows that at +5-μm focus offset, there is a moderate foot, but vertical walls at the top of the photoresist. The best compromise between maintaining critical dimension and sidewall angle control is a -10-μm focus offset.
Figure 4. SEMs of 50-μm diameter copper pillars with 12.5-μm spacing (left) and 50-μm spacing (right).
To examine copper electroplating performance, 50-μm copper pillars were fabricated over a variety of array spacings on a copper-seed substrate. The average pillar height was measured as 30 μm. The pillars show near-vertical sidewall profiles with no signs of underbump plating. Therefore, the photoresist demonstrated adequate durability in the electroplating bath with no adhesion failure. The photoresist was then stripped by soaking in acetone for 10 minutes. Figure 4 shows the resulting copper pillars with 12.5- and 50-μm spacing. There is no indication of copper bridging between adjacent pillars.
A manufacturable copper pillar process requires a photoresist with a rheology to support spin-coating 40- to 100-μm-thick layers in a single application, and sufficient lithographic resolution and process latitude. After exposure and development, the photoresist layer needs to possess sufficient durability for electroplating, and then should strip cleanly in an environmentally friendly solvent system.
Resolution down to 15 μm with good process control was demonstrated, as well as good electroplating performance of dense arrays of copper pillars with diameters as small as 30 μm. These feature sizes are more than sufficient to meet the current and anticipated future design requirements of advanced packaging.
The photoresist is Shin-Etsu SIPR 7120 Series. It was exposed on an Ultratech Unity AP300 wafer stepper and electroplated using a Semitool Raider M system.
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WARREN W. FLACK, director of gobal applications; and HA-AI NGUYEN, staff applications engineer; may be contacted at Ultratech, Inc., 3050 Zanker Road, San Jose, CA 95134, 408/321-8835, [email protected]. ELLIOTT CAPSUTO, technical sales manager; and CRAIG McEWEN, technical sales, may be contacted at Shin-Etsu MicroSi, Inc., 10028 S. 51st Street, Phoenix, AZ 85044, 480/893-8898, [email protected].