by Bob Haavind, Editorial Director, Solid State Technology
Over 1600 technologists gathered in Washington, DC, to explore a wide range of innovative ideas at the 2007 International Electron Devices Meeting (IEDM). Boosting performance as the shrink heads below 45nm was the goal of many new CMOS-based schemes. There were 237 papers from all over the globe, about a third of the 695 submitted.
While current mainstream CMOS approaches, using strain engineering and metal/high-k dielectric gates, were covered extensively, there were also a wide range of further out alternatives, suggesting that darts had been tossed at periodic table charts all over the world.
Germanium and silicon germanium (SiGe) were predominant, but there were may other devices incorporating III-V compounds, metal source and drain, and even hints of future circuitry based on carbon rather than Si or Ge. Carbon-based nanoelectronic technology using graphene even won a catchy new name: “pionics.”
A very promising demonstration of how compound semiconductor devices might be integrated onto a silicon substrate was presented by a group from Intel and IQE (Bethlehem, PA). An enhancement-mode quantum well (QW) transistor using indium-gallium-arsenide InGaAs was heterogeneously integrated onto silicon using a composite buffer only 1.3μm thick. The QFET is very promising for high-speed, low-power logic due to high electron mobility and low leakage. This seamless integration of a high-performance QFET suggests that logic blocks of such devices could be coupled with mainstream SiCMOS platforms for future microprocessors, the authors concluded. The quantum well device with an 80nm gate length had a +0.11V threshold voltage with an ION/IOFF ratio of 2150 with a 0.5V gate voltage swing. Sub-threshold slope and drain induced barrier loading (DIBL) were better for enhancement-mode than depletion-mode devices, they reported.
A sub-50nm compound semiconductor high-electron-mobility transistor (HEMT) also set a new speed record, achieving an extrapolated Fmax of over 1THz, as reported by a group from Northrop Grumman Space Technology and the Jet Propulsion Labs (JPL). The extrapolation was based on the successful demo of a 3-stage low-noise millimeter IC amplifier working at 340GHz with over 15dB gain. The authors believe they can achieve 600-700GHz amplifiers with next-generation designs, pushing the limits for military and telecom systems as well as radio astronomy. The InGaAs/InAlAs/InP HEMT incorporates a T-shaped gate as small as 35nm formed using e-beam lithography.
Another record, an ultrahigh blocking voltage of 8300V which could be useful for high-power systems such as hybrid vehicles, was achieved for an AlGaN/GaN heterogeneous transistor (HFET) on sapphire with thick poly-AIN passivation by a group from Matsushita/Panasonic. Via holes were drilled thru the etch-resistant sapphire by a high-powered laser. The device achieves a specific on-state resistance of 186-Ω.cm2 with an Imax of 150mA/mm.
A room-temperature electrically pumped Ge semiconductor laser, potentially useful for light generation for an IC, was developed by a group from National Taiwan U. They used a simple metal-insulator semiconductor (MIS) structure, with a thin (~2nm) tunneling insulator to allow carrier tunneling between an electrode and the semiconductor. A pair of cleaved (111) planes perpendicular to the plane of junction forms a Fabry-Perot cavity. The device is 48μm wide with a 1-2mm cavity length. The authors suggest that the Ge laser could be integrated onto silicon by epi or wafer bonding, and an even better laser may be feasible by taking advantage of the SiGe junction.
Pionics, or graphene nanoelectronics, was the topic of an overflowing session. Walt deHeer of Georgia Institute of Tech. said he was surprised his paper was accepted due to the early phase of this work on deposited hexagonal carbon like that of carbon nanotubes (CNT). The major difference is that CNTs grow in an uncontrolled tangle while the deposited graphene forms thin films on a SiC wafer. In-plane sigma bonds in the carbon form the strongest bonds known but groups of atoms form p-electron orbitals in what is called pibands, hence the name “pionics.” The piband mass is zero, so carrier velocities are independent of energy. In addition to charge and spin, they are characterized by chirality. Successive layers in the hexagonal motif are rotated about 2.5°, so there is little interlayer coupling.
Similar to CNTs, metallic or semiconducting graphene ribbons can be created with the bandgap inversely proportionally to the ribbon width due to quantum confinement. The graphene layers can be patterned using microelectronics techniques to form both transistors and interconnects. Graphene mobilities of 104cm2/Vs have been demonstrated, promising higher speeds and lower power than is possible with silicon, deHeer said.
Obtaining bandgaps suitable for room-temperature operation would require nanopatterning beyond present capabilities, however, so a chemical modification method for bandgap control would more expedient at present, he explained.
The excitement about pionics at IEDM is shared by DARPA, according to a source at the session, and a major development program is planned for this emerging technology.
Another graphene paper from the U. of Florida in the US, and U. of Pisa in Italy, did a performance comparison of two types of graphene nanoribbon devices: schottky barrier and MOSFETs. The MOSFET has superior parameters and would be less impacted by potential defects, so this type of device would be preferable.
The JJ Ebers award fittingly went to Stephen J. Pearton, a Tasmanian with a dry wit, who was a pioneer in developing processes for compound semiconductors when at Bell Labs. Pearton noted in his acceptance that compound semiconductors and silicon technology now appear to be merging to some extent, and he congratulated the silicon community for “catching up.” — B.H.